Data processing system with microprocessor/cache chip set directly coupled to memory bus of narrower data width

Abstract

A cache of a CPU/cache chip set, has a wide data path that is directly coupled, to a memory data bus having a narrow data path. The coupling is effected by a data transfer path comprising only conductors without any additional components that would introduce signal propagation delays. Cache data transfers are initiated by a cache controller. A bus controller provides data transfer control signals to transfer sets of data where each set has the same number of bits as the width of the memory bus. Data is transferred in burst cycles comprising a plurality of cache data transfer cycles. Each of the latter cycles comprises a plurality of memory bus cycles.

What is claimed is: 
     
       1. Data processing apparatus comprising: a memory subsystem comprising an addressable, a memory bus having a plurality of "n" data bit lines, and a memory controller connected between said RAM and said memory bus for controlling access thereto, said memory controller transferring "n" data bits in each memory bus cycle;   a CPU/cache chip set including a cache memory having a data path width of "m" bits, where "m" is greater than "n" and having a the ratio of "m" to "n" that is an integer "r", said cache memory having "m" cache data lines through which data bit signals are transmitted into and out of said cache memory;   a data transfer path extending between said cache memory and said memory bus, said path consisting of "m" conductors corresponding to respective bits of an "m" in bit word, each conductor having a first end and a second end, each conductor having its first end directly connected to a different one of said cache data lines, said conductors being arranged into "r" groups of "n" conductors with each conductor in each group corresponding to a respective "n" bit subset of the "m" bits and having its second end connected to a different data bit line of said memory bus so that each data bit line of said memory bus is directly connected to "r" data transfer path conductors; and   control means connected between said CPU/cache chip set and said memory bus for controlling direct cache data transfers between said RAM and said cache memory, said control means being operative, for each such cache data transfer, to transfer, sequentially, "r" data sets with "n" data bits in each data set said control means producing signals coordinating direct transfers of "n" bit subsets at said cache with respective "n" bit memory bus cycle transfers, said data sets being transferred over said memory bus one data set per memory bus cycle.   
     
     
       2. Data processing apparatus in accordance with claim 1 wherein said control means comprises: a bus controller connected to said cache memory for initiating "r" memory bus cycles for each cache data transfer; and   logic means connected to said bus controller and to said cache memory for controlling direct sequential gating of "r" data sets of "n" bits to respective portions of "m" bit of cache memory during each cache data transfer.   
     
     
       3. Data processing apparatus in accordance with claim 2 wherein: said bus controller generates a first signal identifying which data group is being transferred in each memory bus cycle, a second signal defining when data is valid on said data transfer path, and a third signal identifying completion of cache data transfers; and   said logic means generates a plurality of signals in response to said first, second, and third signals from said bus controller, said plurality of signals including "r" strobing signals for strobing said data sets,   "r" steering signals for steering data sets into respective subsets of the "m" bits of said cache memory during write cache data transfers, and   completion signals notifying said cache memory of completion of data transfer.     
     
     
       4. Data processing apparatus comprising: a microprocessor;   a dual ported cache having one port connected to said microprocessor for transferring data therebetween, said cache having a second port provided with "m" cache data lines through which cache data bits are transmitted into and out of said cache in response to strobe signals;   a cache controller connected to said microprocessor and to said cache;   a memory for storing data which is read from and written to the memory bus in response to strobe signals;   a memory bus comprising "n" bit lines where "n" is less than "m" having a ratio of "m" to "n" that is an integer "r";   a memory controller connected between said memory and said memory bus for controlling access to said memory, said memory controller producing memory bus cycles and transmitting "n" data bits in each memory bus cycle;   a cache data bus connected between said second port of said cache and said memory bus for transferring data between said memory and said cache, said cache data bus having "m" conductors, each conductor having a first end and a second end, each conductor having its first end connected to a different one of said cache data lines, said conductors being arranged into "r" groups of "n" conductors with each conductor in each group having its second end connected to a different data bit line of said memory bus so that each data bit line of said memory bus is directly connected to "r" conductors;   control means connected to said cache controller, to said memory bus, and to said cache for coordinating strobe signals transfer of cache data between said memory and said cache, said control means being operative, to produce control signals for each data transfer, to sequentially transfer "r" data sets with "n" data bits in each data set directly to a respective group of cache data lines so that, said data sets are transferred over said memory bus to said cache one data set per memory bus cycle.   
     
     
       5. Data processing apparatus in accordance with claim 4 wherein said control means comprises: a bus controller connected to said cache controller for producing "r" memory bus cycles for each cache data transfer; and logic means connected to said bus controller and to said cache for controlling sequential gating of "r" data sets directly into and out of respective portions of "m" bits of said cache during each cache data transfer.   
     
     
       6. Data processing apparatus in accordance with claim 5 wherein: said bus controller generates a first signal identifying which data group is being transferred in each memory bus cycle, a second signal defining when data is valid on said data transfer path, and a third signal identifying completion of cache data transfers; and   said logic means generates a plurality of signals in response to said first, second, and third signals from said bus controller, said plurality of signals including "r" strobing signals for indicating "n" bit data sets are ready to be transferred,   "r" steering signals for steering respective data sets into corresponding portions of said cache during write cache data transfers, and   completion signals notifying said cache of completion of data transfer.