Clock synchronization scheme for fractional multiplication systems

Abstract

A circuit for synchronizing a multiplied system clock signal includes a device for generating a system clock signal, a first device that receives the system clock signal and generates a synchronization signal and at least one second device that receives the system clock signal and the synchronization signal. Each of the second devices includes a device for multiplying the system clock signal to produce the multiplied system clock signal and a device for synchronizing the multiplied system clock signal with each other multiplied system clock signal produced by the other second devices based on the synchronization signal.

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows: 
     
       1. A circuit for synchronizing a multiplied system clock signal, comprising: means for generating a system clock signal;   a first device, operatively connected to said generating means, for receiving said system clock signal, and for generating a synchronization signal; and   a plurality of second devices, operatively connected to said generating means and said first device, for receiving said system clock signal and said synchronization signal, each of said second devices including a multiplied clock generator circuit for outputting said multiplied system clock signal and for synchronizing said multiplied system clock signal with said system clock signal, such that each said multiplied system clock signal produced by one of said second devices is synchronized and in phase with other multiplied system clock signals produced by other ones of said second devices,   wherein said multiplied system clock signal comprises a non-integer fractional multiple of said system clock signal,   wherein said multiplied clock generator circuit comprises: first and second logic circuits;   a phase/frequency detector circuit coupled to each of said first and second logic circuits; and   an oscillator circuit for receiving an output of said phase/frequency detector circuit, said oscillator circuit including means for outputting said multiplied system clock signal.     
     
     
       2. A circuit as in claim 1, further comprising: a clock tree distribution circuit, operatively connected to said multiplied clock generator circuit, for outputting a feedback clock signal.   
     
     
       3. A circuit as in claim 2, further comprising: a divider circuit operatively connected to said multiplied clock generator circuit,   wherein said divider circuit includes means for dividing said feedback clock signal and means for outputting a divided feedback clock signal to said multiplied clock generator circuit.   
     
     
       4. A circuit as in claim 3, wherein said first logic circuit includes means for comparing said system clock signal and said synchronization signal and means for outputting a first pulse when said system clock signal has a predetermined state and said synchronization signal has said predetermined state, and said second logic circuit including means for comparing said divided feedback clock signal and said multiplied system clock signal and means for outputting a second pulse when said divided feedback clock signal has said predetermined state and said multiplied system clock signal has said predetermined state.   
     
     
       5. A circuit as in claim 4, wherein said phase/frequency detector circuit includes means for comparing said first pulse and said second pulse and means for controlling said oscillator circuit so that said first pulse and said second pulse are produced substantially simultaneously and said multiplied system clock signal is synchronized with said other multiplied system clock signals of said others of said second devices. 
     
     
       6. A circuit as in claim 1, wherein said first and second logic circuits each comprise an AND circuit. 
     
     
       7. A circuit as in claim 1, wherein said multiplied clock generator circuit further comprises a low pass-filter operatively connected to said oscillator circuit and said phase/frequency detector circuit. 
     
     
       8. A circuit as in claim 3, wherein said divider circuit further comprises a plurality of latch circuits, wherein said divider circuit performs a plurality of division operations on said feedback clock signal. 
     
     
       9. A circuit for synchronizing a multiplied system clock signal comprising: means for generating a system clock signal;   a first device, operatively connected to said generating means for receiving said system clock signal and for generating a synchronization signal; and   a plurality of second devices, operatively connected to said generating means and said first device, for receiving said system clock signal and said synchronization signal, each of said second devices including a multiplied clock generator circuit for outputting said multiplied system clock signal and for synchronizing said multiplied system clock signal with said system clock signal, such that each said multiplied system clock signal produced by one or said second devices is synchronized and in phase with other multiplied system clock signals produced by other ones of said second devices,   wherein said multiplied system clock signal comprises a non-integer fractional multiple of said system clock signal,   wherein said first device comprises a second multiplied clock generator circuit including: third and fourth logic circuits;   a second phase/frequency detector circuit coupled to each of said third and fourth logic circuits; and   a second oscillator circuit for receiving an output of said second phase/frequency detector circuit.     
     
     
       10. A circuit as in claim 1,wherein said non-integer fractional multiple comprises a number greater than one.