Method and apparatus for generating four phase non-over lapping clock pulses for a charge pump

Abstract

A clock generation circuit which includes a first circuit for generating first and second trains of non-overlapping and opposite phase clock pulses from an input train of clock pulses, and second and third circuits each for generating a pair of non-overlapping and opposite phase trains of clock pulses from one of the first or second trains of opposite phase clock pulses provided by the first circuit.

What is claimed is: 
     
       1. A clock generation circuit comprising: a first circuit for generating a first train and a second train of non-overlapping and opposite phase clock pulses from an input train of clock pulses;   a second circuit for generating a third train and a fourth train of non-overlapping and opposite phase clock pulses from the first train of clock pulses generated by the first circuit; and   a third circuit for generating a fifth train and a sixth train of non-overlapping and opposite phase clock pulses from the second train of clock pulses generated by the first circuit, wherein the third train of clock pulses and the fifth train of clock pulses are non-overlapping phase clock pulses.   
     
     
       2. A clock generation circuit as claimed in claim 1 where the non-overlapping phase clock pulses are non-overlapping during a first time of the clock pulses and are overlapping during a second time of the clock pulses. 
     
     
       3. A clock generation circuit as claimed in claim 2 in which the first, second, and third circuits each comprise first and second NAND gates, conductors for providing the input train of clock pulses to the first NAND gate and the inverted input train of clock pulses to the second NAND gate, and circuitry for providing the output of each NAND gate to the input of the other NAND gate through a delay circuit. 
     
     
       4. A clock generation circuit as claimed in claim 3 in which the width of individual pulses of each of the trains of clock pulses may be varied by varying a delay provided by each of the delay circuits. 
     
     
       5. A charge pump circuit comprising a charge pump having a plurality of stages,   each of the stages including a first transistor device adapted to transfer charge between stages,   a second transistor device adapted to precharge an input terminal of the first transistor device, and   an interstage capacitor for storing charge transferred by the first transistor device; and   a clock generation circuit comprising: a first circuit for generating a first train and a second train of non-overlapping and opposite phase clock pulses from an input train of clock pulses;   a second circuit for generating a third train and a fourth train of non-overlapping and opposite phase clock pulses from the first train of clock pulses generated by the first circuit; and   a third circuit for generating a fifth train and a sixth train of non-overlapping and opposite phase clock pulses from the second train of clock pulses generated by the first circuit, where the third train of clock pulses and the fifth train of clock pulses are non-overlapping phase clock pulses.     
     
     
       6. A clock generation circuit as claimed in claim 5 where the non-overlapping phase clock pulses are non-overlapping during a first time of the clock pulses and are overlapping during a second time of the clock pulses. 
     
     
       7. A computer system comprising: a central processor;   a system bus;   main memory; and   programmable non-volatile long term storage including: a flash EEPROM memory array, and   a charge pump circuit for furnishing voltages for operating the flash EEPROM memory array comprising: a charge pump having a plurality of stages, each of the stages including a first transistor device adapted to transfer charge between stages,   a second transistor device adapted to precharge an input terminal of the first transistor device, and   an interstage capacitor for storing charge transferred by the first transistor device; and       a clock generation circuit comprising a first circuit for generating a first train and a second train of non-overlapping and opposite phase clock pulses from an input train of clock pulses;   a second circuit for generating a third train and a fourth train of non-overlapping and opposite phase clock pulses from the first train of clock pulses generated by the first circuit; and   a third circuit for generating a fifth train and a sixth train of non-overlapping and opposite phase clock pulses from the second train of clock pulses generated by the first circuit, where the third train of clock pulses and the fifth train of clock pulses are non-overlapping phase clock pulses.       
     
     
       8. A computer system as claimed in claim 7 in which the non-overlapping phase clock pulses are non-overlapping during a first time of the clock pulses and are overlapping during a second time of the clock pulses. 
     
     
       9. A clock generation circuit comprising a first means for generating a first train and a second train of non-overlapping and opposite phase clock pulses from an input train of clock pulses;   a second means for generating a third train and a fourth train of non-overlapping and opposite phase clock pulses from the first train of clock pulses generated by the first means; and   a third means for generating a fifth train and a sixth train of non-overlapping and opposite phase clock pulses from the second train of clock pulses generated by the first means, where the third train of clock pulses and the fifth train of clock pulses are non-overlapping phase clock pulses.   
     
     
       10. A clock generation circuit as claimed in claim 9 in which the non-overlapping phase clock pulses are non-overlapping during a first time of the clock pulses and are overlapping during a second time of the clock pulses. 
     
     
       11. A charge pump circuit comprising charge pump means having a plurality of stages, each of the stages including a first transistor means adapted to transfer charge between stages,   a second transistor means adapted to precharge an input terminal of the first transistor means, and   interstage means for storing charge transferred by the first transistor means; and   a clock generation circuit comprising a first means for generating a first train and a second train of non-overlapping and opposite phase clock pulses from an input train of clock pulses;   a second means for generating a third train and a fourth train of non-overlapping and opposite phase clock pulses from the first train of clock pulses generated by the first means; and   a third means for generating a fifth train and a sixth train of non-overlapping and opposite phase clock pulses from the second train of clock pulses generated by the first means, where the third train of clock pulses and the fifth train of clock pulses are non-overlapping phase clock pulses.       
     
     
       12. A charge pump circuit as claimed in claim 11 in which the non-overlapping phase clock pulses are non-overlapping during a first time of the clock pulses and are overlapping during a second time of the clock pulses. 
     
     
       13. A computer system comprising: central processing means;   bus means;   main memory means; and   means for providing programmable non-volatile long term storage, the last mentioned means including: flash EEPROM memory array means, and   a charge pump circuit for furnishing voltages for operating the flash EEPROM memory array comprising:   charge pump means having a plurality of stages, each of the stages including a first transistor means adapted to transfer charge between stages,   a second transistor means adapted to precharge an input terminal of the first transistor means, and interstage means for storing charge transferred by the first transistor means; and     a clock generation circuit comprising a first means for generating a first train and a second train of non-overlapping and opposite phase clock pulses from an input train of clock pulses;   a second means for generating a third train and a fourth train of non-overlapping and opposite phase clock pulses from the first train of clock pulses generated by the first means; and   a third means for generating a fifth train and a sixth train of non-overlapping and opposite phase clock pulses from the second train of clock pulses generated by the first means, where the third train of clock pulses and the fifth train of clock pulses are non-overlapping phase clock pulses.       
     
     
       14. A computer system as claimed in claim 13 in which the non-overlapping phase clock pulses are non-overlapping during a first time of the clock pulses and are overlapping during a second time of the clock pulses. 
     
     
       15. A method for generating clock pulses comprising the steps of: generating a first train and a second train of non-overlapping and opposite phase clock pulses from an input train of clock pulses;   generating a third train and a fourth train of non-overlapping and opposite phase clock pulses from the first train of clock pulses; and   generating a fifth train and a sixth train of non-overlapping and opposite phase clock pulses from the second train of clock pulses, where the third train of clock pulses and the fifth train of clock pulses are non-overlapping phase clock pulses.   
     
     
       16. A method for generating clock pulses as claimed in claim 15 in which the non-overlapping phase clock pulses are non-overlapping during a first time of the clock pulses and are overlapping during a second time of the clock pulses.