High-power amplifier using parallel transistors

Abstract

An input radio frequency signal to be amplified is fed to the gate terminals of parallel field effect power transistors through impedance matching networks that comprise parallel resistor-capacitor combinations. The capacitor is selected so that it is self-resonant at the frequency of operation, thereby preventing attenuation of the input signal at that frequency. A shunt resistor is coupled between the gates of the parallel transistors to eliminate odd mode oscillations.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows: 
     
       1. An amplifier circuit for amplifying an input signal comprising: a pair of transistors each having a first and second terminal between which an amplified current is conducted and a control terminal that controls an amount of current conducted between the first and second terminal, wherein the first terminals of each transistor of the pair of transistors are coupled together;   a pair of parallel matching networks each comprising a resistor and capacitor connected in parallel, each parallel matching network of the pair being disposed between and in series with the control terminal of one of the transistors of the pair of transistors and the input signal, the resistor and capacitor of each parallel matching network cooperating to attenuate input signals both above and below a frequency of interest, while allowing input signals at the frequency of interest to reach the transistor substantially unattenuated; and   a bypass resistor coupled between the control terminals of the pair of transistors, the bypass resistor having a resistance such that unbalanced modes are rejected.   
     
     
       2. The amplifier of claim 1, wherein the bypass resistor has a resistance selected to be approximately two to ten times an input impedance of the pair of transistors. 
     
     
       3. The amplifier of claim 1, wherein the pair of transistors are MOSFETs. 
     
     
       4. The amplifier of claim 1, wherein the input signal has a fundamental frequency and wherein the capacitor of the parallel matching networks is self-resonant at the fundamental frequency of the input signal. 
     
     
       5. An amplifier circuit for amplifying an input signal comprising; a plurality of transistors each having a first and second terminal between which an amplified current is conducted and a control terminal that controls an amount of current conducted between the first and second terminals, wherein the first terminals of each transistor of the plurality of transistors are coupled together;   a plurality of parallel matching networks each comprising a resistor and capacitor connected in parallel, each parallel matching network of the plurality of parallel matching networks being disposed between and in series with a control terminal of one of the plurality of transistors and the input signal, the resistor and capacitor of each parallel matching network cooperating to attenuate input signals both above and below the frequency of interest, while allowing the input signal to reach the transistor substantially unattenuated; and   a bypass resistor coupled between the control terminals of each transistor of the plurality of transistors, the bypass resistor having a resistance such that unbalanced modes are rejected.