P
US5699017AExpiredUtilityPatentIndex 74

Automatic gain control circuit

Assignee: YAMAHA CORPPriority: Mar 27, 1995Filed: Mar 26, 1996Granted: Dec 16, 1997
Est. expiryMar 27, 2015(expired)· nominal 20-yr term from priority
Inventors:MAEJIMA TOSHIO
H03G 1/007H03G 3/3015
74
PatentIndex Score
15
Cited by
3
References
2
Claims

Abstract

An automatic gain control circuit is provided, which has minimum variations in the output signal level even with the presence of variations in component parts thereof and the temperature dependency of component parts thereof and can therefore dispense with the use of an additional amplifier circuit for adjusting the output level. An input signal-attenuating circuit attenuates the level of an input signal to a voltage amplifier circuit. An output level-detecting circuit detects the voltage level of an output signal from the voltage amplifier circuit to thereby carry out feedback control by controlling the attenuating characteristic of the input signal-attenuating circuit in response to the detected voltage of the output signal such that the voltage level of the output signal from the voltage amplifier circuit is maintained at a constant level. The output level-detecting circuit is comprised of a differential amplifier circuit which detects and amplifies the difference between a predetermined reference voltage and the voltage of the output signal from the voltage amplifier circuit.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An automatic gain control circuit comprising: a voltage amplifier circuit including an operational amplifier having an input terminal and an output terminal;   a direct current bias terminal that applies a predetermined direct current bias to said voltage amplifier circuit;   an input signal-attenuating circuit including an input resistance serially connected to said input terminal of said voltage amplifier circuit, and a MOS transistor connected between said input terminal of said voltage amplifier circuit and said direct current bias terminal, said MOS transistor having a gate;   a current mirror type differential amplifier circuit having an input terminal thereof connected to said output terminal of said voltage amplifier circuit, and another input terminal thereof disposed to be supplied with a predetermined reference voltage which is lower than a voltage of said predetermined direct current bias from said direct current bias terminal, said differential amplifier circuit having an output terminal for outputting an output which is inverted when a voltage level of said output signal from said voltage amplifier circuit lowers below said predetermined reference voltage; and   a time constant circuit having an input terminal thereof connected to said output terminal of said differential amplifier circuit, and an output terminal thereof connected to said gate of said MOS transistor of said input signal-attenuating circuit, said time constant circuit being responsive to said output from said differential amplifier circuit, that delivers a control signal to said gate of said MOS transistor of said input signal-attenuating circuit to thereby cause progressive decrease of on-state resistance of said MOS transistor when said output from said differential amplifier circuit is inverted.   
     
     
       2. An automatic gain control circuit as claimed in claim 1, further including a back bias terminal, and wherein said MOS transistor of said input signal-attenuating circuit has a substrate region, said back bias terminal supplying a back bias to said substrate region of said MOS transistor.

Cited by (0)

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References (0)

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