Adiabatic MOS logic and power supplying method and apparatus

Abstract

A plurality of stages of MOS gate circuits are connected in series and are driven with a 2-phase AC power source. The alternating speed of the power source is slower than the operation speed of internal circuit elements of the MOS gate circuits. A cutoff device such as a transistor is arranged on each side of each of the MOS gate circuits and is connected to the power source. The cutoff devices of each MOS gate circuit are conductive only when one phase of the power source is at high potential and the other at low potential. When the MOS gate circuit of a given stage (N i ) is inactive, the MOS gate circuit of the next stage (N i+1 ) holds charge, to reduce an energy loss.

What is claimed is: 
     
       1. A MOS gate circuit comprising: a) a first internal circuit having first internal circuit elements each made of a MOS transistor, and a first and a second power supply terminals for connecting a source voltage to the first internal circuit elements;   b) a first cutoff means having a first end connected to the first power supply terminal;   c) a second cutoff means having a first end connected to the second power supply terminal;   d) a first AC power source having a first phase and connected to a second end of the first cutoff means; and   e) a second AC power source having a second phase and connected to a second end of the second cutoff means, the alternating speed of the first and second AC power sources being slower than the operation speed of the first internal circuit elements,   the first and second phases being opposite to each other, and   the first internal circuit elements being conductive only when the first phase is at high potential.     
     
     
       2. A circuit as claimed in claim 1, further comprising: f) a second internal circuit having a second internal circuit elements electrically coupled with the first internal circuit elements, and a third and a fourth power supply terminals for connecting a source voltage to the second internal circuit elements;   g) a third cutoff means having a first end connected to the third power supply terminal; and   h) a fourth cutoff means having a first end connected to the fourth power supply terminal, a second end of the third cutoff means being connected to the second AC power source, and a second end of the fourth cutoff means being connected to the first AC power source.     
     
     
       3. A circuit as claimed in claim 2, wherein the second internal circuit elements are not conductive when the first internal circuit elements are conductive. 
     
     
       4. A circuit as claimed in claim 1, wherein each of the first and second cutoff means is a MOS transistor, the gate electrode of the MOS transistor being connected to one of the source and drain electrodes thereof. 
     
     
       5. A circuit as claimed in claim 1, wherein each of the first and second cutoff means is a diode. 
     
     
       6. A circuit as claimed in claim 1, wherein the first internal circuit and first and second cutoff means are partly or wholly made of SOI elements. 
     
     
       7. A circuit as claimed in claim 1, wherein the first internal circuit elements are MOS gate circuits that are cascaded to one another and are each electrically coupled with the first and second cutoff means. 
     
     
       8. A circuit as claimed in claim 7, wherein the MOS gate circuits are collectively operated in response to a single clock. 
     
     
       9. A circuit as claimed in claim 1, further comprising a first DC power source connected in series to said first AC power source, and a second DC power source connected in series to said second AC power source. 
     
     
       10. A MOS gate circuit comprising: a) an internal circuit composed of a MOS transistor expressed with an equivalent resistor R and an equivalent capacitor C connected in series;   b) an inductance L connected in parallel with the internal circuit at connecting points; and   c) an external AC power source for supplying a predetermined voltage between one of said connecting points of the inductance L and the internal circuit and another connecting point thereof,   wherein the frequency f o  of the external AC power source is expressed as follows: ##EQU8## wherein charging and discharging currents from the external AC power source to the internal circuit are absorbed and canceled by the inductance L.   
     
     
       11. A circuit as claimed in claim 10, wherein a value of √LC is greater than a time constant of τ=RC. 
     
     
       12. A power supplying method of a MOS gate circuit, comprising the steps of: forming an LCR resonance circuit by adding an inductance L in parallel with an internal circuit made of a MOS transistor, the internal circuit being expressed as an RC series circuit composed of an equivalent resistor R and an equivalent capacitor C connected in series; and   driving the internal circuit by applying a voltage between one of the connecting points of the internal circuit and the inductance L and another connecting point thereof, said voltage being supplied by an AC power source having a resonance frequency of the LCR resonance circuit, so that charging and discharging currents from the AC power source to the internal circuit are absorbed by the inductance L.   
     
     
       13. A power supplying method of a MOS gate circuit comprising an internal circuit having internal circuit elements, the internal circuit operating between high and low level supply voltages, comprising the step of supplying the internal circuit with an alternating source voltage defined as a difference between the high and low level supply voltages, the period of the alternating source voltage being longer than the gate delay time of the internal circuit elements, wherein phases of the high and low level supply voltages are opposite to each other. 
     
     
       14. A method as claimed in claim 13, wherein the alternating source voltage is made of a sinusoidal waveform. 
     
     
       15. A method as claimed in claim 13, wherein the alternating source voltage is substantially made of a rectangular waveform whose rise time and fall time are each longer than the gate delay time. 
     
     
       16. A method as claimed in claim 15, wherein the alternating source voltage has a ramp waveform portion that rises at a predetermined inclination. 
     
     
       17. A method as claimed in claim 15, wherein the rise time is 5 to 20 times longer than the gate delay time. 
     
     
       18. A method as claimed in claim 13, wherein the alternating source voltage is composed of a couple of alternating voltages whose phases are shifted from each other by π. 
     
     
       19. A method as claimed in claim 13, wherein the MOS gate circuit comprises a sequence of the internal circuits cascaded to one another, and wherein said supplying step comprises the step of supplying a couple of alternating voltages whose phases are shifted from each other by π to the internal circuits so that, when one of the internal circuits is active, the next internal circuit is inactive. 
     
     
       20. A MOS gate circuit comprising: a) a first pMOS circuit having a first and a second power supply terminals;   b) a first nMOS circuit having a third and a fourth power supply terminals;   c) a first cutoff means having a first and a second end, the first end connected to the second power supply terminals;   d) a second cutoff means having a third and a fourth end, the third and connected to the third power supply terminals; and the fourth end connected to the second end of the first cutoff means;   e) a first AC power source having a first phase and connected to the first power supply terminals; and   f) a second AC power source having a second phase and connected to the fourth power supply terminals,   wherein the alternating speed of the first and second AC power sources being slower than the operation speed of the first pMOS and CMOS circuits, the first and second phases being opposite to each other, and   the first pMOS circuit being conductive only when the first phase being at high potential.     
     
     
       21. A circuit as claimed in claim 20, further comprising; g) a second pMOS circuit having a fifth and a sixth power supply terminals;   h) a second nMOS circuit having a seventh and an eighth power supply terminals;   i) a third cutoff means having a fifth and a sixth end, the fifth end connected to the sixth power supply terminals; and   j) a fourth cutoff means having a seventh and an eighth end, the seventh end connected to the seventh power supply terminals, and the eighth end connected to the sixth end;   wherein the fifth power supply terminals connected to said second AC power source, and the eighth power supply terminals connected to said first AC power source.   
     
     
       22. A circuit as claimed in claim 20, wherein the second pMOS circuit is not conductive then the first pMOS circuit is conductive.