Internal voltage boosting method and circuit for a semiconductor memory device

Abstract

An internal voltage boosting circuit for a semiconductor memory device comprises first and second boosted voltage generators for boosting an internal voltage of said memory device. A voltage level detector is operative to detect the internal voltage. A first logic circuit is operatively connected to the first generator and to the voltage level detector. The logic circuit activates the first generator when (a) the detected voltage falls below a predetermined voltage and (b) the memory device is in an active state. A second logic circuit is operatively connected to the second generator. The second logic circuit activates the second generator when said memory device is in a precharge state.

I claim: 
     
       1. An internal voltage boosting circuit for a semiconductor device comprising: a master signal generator, said generator generating a master signal responsive to a row address strobe signal;   a first controller, said first controller generating a first control signal in response to said master signal;   an inverting gate operatively connected to said master signal generator for inverting said master signal;   a second controller operatively connected to said inverting gate, said second controller generating a second control signal in response to said inverted master signal;   a third controller operatively connected to said master signal generator, said third controller generating a third control signal in response to said master signal;   a level detector for detecting the level of an internal boosted voltage in response to said first and third control signals and generating a detection signal if said detected signal level is less than a predetermined level;   a fourth controller operatively connected to said level detector, said fourth controller generating a fourth control signal in response to said detection signal;   a fifth controller, said fifth controller generating a fifth control signal in response to said first and fourth control signals;   a first boosted voltage generator operatively connected to said fifth controller, said first boosted voltage generator generating a first boosted voltage in response to said fifth control signal; and a second boosted voltage generator operatively connected to said second controller, said second boosted voltage generator generating a second boosted voltage in response to said second control signal.   
     
     
       2. An internal voltage boosting circuit for a semiconductor device as claimed in claim 1 wherein said level detector includes a gate for receiving said third control signal immediately after the activation of said first control signal, and a detector for detecting the level of said internal boosted voltage in response to said third control signal having passed through said gate. 
     
     
       3. An internal voltage boosting circuit of a semiconductor device as claimed in claim 1, wherein said fourth controller includes: an oscillator for generating a predetermined oscillating signal in response to said detection signal; and   an output stage for synthesizing said oscillating signal and said detection signal.   
     
     
       4. An internal voltage boosting circuit of a semiconductor device comprising: first signal generating means for generating a first enabling signal in an initial active period of a row address strobe signal;   second signal generating means for generating a second enabling signal in an initial precharge period of said row address strobe signal;   level detecting means for generating a detection signal activated when the level of an internal boosted voltage is less than a predetermined level, in response to an active period of said first enabling signal and said row address strobe signal;   third signal generating means for generating a third enabling signal in response to said detection signal and first enabling signal;   first boosted voltage generating means for generating a first boosted voltage in response to said third enabling signal; and   second boosted voltage generating means for generating a second boosted voltage in response to said second enabling signal.   
     
     
       5. A method for operating a semiconductor memory device of the type having a plurality of address lines which require a boosted voltage during a precharge period and during an active period, said method comprising: detecting a voltage level during an active period of the memory derive;   boosting the detected voltage level each time the detected level falls below a predetermined voltage level; and   boosting the voltage level during a precharge period of the memory device.   
     
     
       6. The method of claim 5 wherein boosting the detected voltage level each time the detected level falls below a predetermined voltage level is performed by a boosted voltage generator. 
     
     
       7. The method of claim 6 wherein boosting the voltage level during a precharge period of the memory device is performed by a second boosted voltage generator. 
     
     
       8. An internal voltage boosting circuit for a semiconductor memory device comprising: a first boosted voltage generator for boosting an internal voltage of said memory device;   a second boosted voltage generator for boosting said internal voltage;   a voltage level detector operative to detect said internal voltage;   a first logic circuit operatively connected to said first generator and to said voltage level detector, said logic circuit activating said first generator when (a) the detected voltage falls below a predetermined voltage and (b) the memory device is in an active state; and   a second logic circuit operatively connected to said second generator, said second logic circuit activating said second generator when said memory device is in a precharge state.