Method and apparatus for executing nested loops in a digital signal processor

Abstract

A digital signal processing system for executing instructions, including a program memory which stores the instructions and a program control unit for receiving and processing a sequence of the instructions to generate control signals for controlling operation of the system, and a loop circuit for use in such a program control unit. The loop circuit controls execution of a loop (preferably a nested loop) of a sequence of the instructions. Preferably, the loop circuit includes loop registers for storing loop start and end addresses and loop count values, and logic circuitry for implementing loops (including nested loops) in response to the addresses and count values in the loop registers. The loop circuit is initialized by loading appropriate addresses and values into the loop registers. After initialization, the loop circuit executes true zero overhead nested loops of instructions in the sense that the instructions to be looped need not include any initialization instructions, any special instruction to indicate the start of a loop or any dedicated branch instruction at the end of a loop for branching back to the start. Preferably, the loop circuit includes an end address comparator and circuitry for disabling this comparator when the loop circuit is not executing a loop to reduce circuit power consumption. Other aspects of the invention are methods of operating such a digital signal processor, and such a loop circuit.

What is claimed is: 
     
       1. A digital signal processing system, for executing instructions and thereby processing data, said system including: a program memory which stores the instructions; and   program control means for receiving a sequence of the instructions from the program memory and generating control signals for controlling execution of the instructions in said sequence, wherein the program control means includes a loop circuit for causing the program control means to execute a nested loop of the instructions, wherein the nested loop includes an inner loop and an outer loop, and wherein the loop circuit includes:   a first set of loop registers for storing first loop start and end addresses and loop count values for the inner loop;   a second set of loop registers for storing therein second loop start and end addresses and loop count values for the outer loop;   logic circuitry for controlling execution of the nested loop using the addresses and loop count values in the loop registers, in response to a loop enable signal;   a first end address comparator for comparing addresses corresponding to instructions of the inner loop against the first loop end address; and   a second end address comparator for comparing addresses corresponding to instructions of the outer loop against the second loop end address.   
     
     
       2. The system of claim 1, wherein the first set of loop registers includes a first current count register and a first loop repeat count register, and wherein the logic circuitry includes: means for loading the first current count register with a value preloaded in the first loop repeat count register, in response to a first signal indicating a final repetition of the inner loop and a second signal indicating that the program control means has been set to assert a last instruction of the inner loop.   
     
     
       3. The system of claim 2, wherein the second set of loop registers includes a second current count register and a second loop repeat count register, and wherein the logic circuitry includes: means for loading the second current count register with a value preloaded in the second loop repeat count register, in response to a signal indicating a final repetition of the outer loop and a signal indicating that the program control means has been set to assert a last instruction of the outer loop.   
     
     
       4. The system of claim 1, wherein the logic circuitry also includes: means for asserting disabling bits to the first end address comparator and the second end address comparator following execution of the nested loop.   
     
     
       5. A loop circuit for controlling execution of a nested loop by a digital signal processing system, where the digital signal processing system includes a program control means for receiving a sequence of instructions from a program memory and generating control signals for controlling execution of the instructions in said sequence, wherein the nested loop includes an inner loop of a sequence of the instructions and an outer loop of another sequence of the instructions, said loop circuit including: a first set of loop registers for storing loop start and end addresses and loop count values for the inner loop;   a second set of loop registers for storing therein loop start and end addresses and loop count values for the outer loop;   logic circuitry for controlling execution of the nested loop using the addresses and loop count values in the loop registers, in response to a loop enable signal;   a first end address comparator for comparing addresses corresponding to instructions of the inner loop against the first loop end address; and   a second end address comparator for comparing addresses corresponding to instructions of the outer loop against the second loop end address.   
     
     
       6. The loop circuit of claim 5, wherein the first set of loop registers includes a first current count register and a first loop repeat count register, and wherein the logic circuitry includes: means for loading the first current count register with a value preloaded in the first loop repeat count register, in response to a first signal indicating a final repetition of the inner loop and a second signal indicating that the program control means has been set to assert a last instruction of the inner loop.   
     
     
       7. The loop circuit of claim 6, wherein the second set of loop registers includes a second current count register and a second loop repeat count register, and wherein the logic circuitry includes: means for loading the second current count register with a value preloaded in the second loop repeat count register, in response to a signal indicating a final repetition of the outer loop and a signal indicating that the program control means has been set to assert a last instruction of the outer loop.   
     
     
       8. The loop circuit of claim 5, wherein the logic circuitry also includes: means for asserting disabling bits to the first end address comparator and the second end address comparator following execution of the nested loop.   
     
     
       9. A loop circuit for controlling execution of a nested loop by a digital signal processing system, where the digital signal processing system includes a program control means, having an associated program count register, said program control means for receiving a sequence of instructions from a program memory and generating control signals for controlling execution of the instructions in said sequence, wherein the nested loop includes an inner loop of a sequence of the instructions and an outer loop of another sequence of the instructions, said loop circuit including: a first set of loop registers for the inner loop comprising a first loop current count register for storing therein a first loop current count value, a first loop repeat count register for storing therein a first loop repeat count value, a first loop start register for storing therein a first loop start value, and a first loop end register for storing therein a first loop end address value;   a second set of loop registers for the outer loop comprising a second loop current count register for storing therein a second loop current count value, a second loop repeat count register for storing therein a second loop repeat count value, a second loop start register for storing therein a second loop start value, and a second loop end register for storing therein a second loop end address value;   means for automatically reloading the first loop current count register with the value stored in the first loop repeat count register, in the event the value in the first loop current count register equals zero and the address value in the program count register is equal to the value stored in the first loop end register; and   means for automatically reloading the second loop current count register with the value stored in the second loop repeat count register, in the event the value in the second loop current count register equals zero and to halt the loop operation in the event the address value in the program count register is equal to the value stored in the second loop end register.