Synchronous stress test control

Abstract

The present invention ensures that the entire data path of the synchronous integrated circuit device composed of master and slave latches is initialized upon power-up in a test mode, thereby overcoming a prior art problem of non-initialization of the device data path. In the test mode, the master clock signal is initialized internally to the synchronous integrated circuit device to allow the master latch to conduct. A clock signal which is a derivative of a master clock signal is controlled to be equal to a first logic state in order to control a slave latch element of the synchronous integrated circuit device to conduct, regardless of the state of the master clock signal. Controlling the clock signal to be equal to the first logic state allows the clock signal to be able to control the slave latch element so that entire data path of the integrated circuit device is initialized upon power-up of the device in the test mode. The logic state of the clock signal is controlled by a clock control circuit which sets the logic state of the clock as a function of whether the device is in a test mode. Thus, the master clock signal which controls the master latch element and the clock signal which controls the slave latch element are controlled such that the master latch and the slave latch conduct simultaneously for proper and full initialization of the device data path upon power-up of the device in a test mode.

What is claimed is: 
     
       1. A method of initializing the data path of an integrated circuit device, comprising the steps of: controlling a first clock signal to cause conduction of a master element of the integrated circuit device during a test mode of the integrated circuit device; and   controlling a second clock signal to cause conduction of a slave element of the integrated circuit device during the test mode of the integrated circuit device;   wherein the master element and the slave element conduct simultaneously to initialize the data path of the integrated circuit device.   
     
     
       2. The method of claim 1, wherein the master element and the slave element conduct simultaneously to initialize the data path of the integrated circuit device upon power-up of the integrated circuit device in the test mode. 
     
     
       3. The method of claim 2, wherein the master element and the slave element conduct simultaneously for the duration of the test mode. 
     
     
       4. The method of claim 1, wherein the test mode is entered upon power-up of the integrated circuit device. 
     
     
       5. The method of claim 1, wherein the data path is initialized internal to the integrated circuit device. 
     
     
       6. The method of claim 1, wherein the second clock signal is controlled to cause conduction of the slave latch element regardless of a logic state of the first clock signal. 
     
     
       7. The method of claim 6, wherein the second clock signal is controlled to cause conduction of the slave latch element by a clock control circuit. 
     
     
       8. The method of claim 1, wherein the first clock signal is a master clock signal and the second clock signal is a derivative signal of the master clock signal. 
     
     
       9. The method of claim 8, wherein the master clock signal is a signal external to the integrated circuit device. 
     
     
       10. The method of claim 1, wherein the integrated circuit device is a synchronous integrated circuit device. 
     
     
       11. The method of claim 1, wherein the master element is a master latch element and the slave element is a slave latch element. 
     
     
       12. The method of claim 1, wherein the master element is a master flip-flop element and the slave element is a slave flip-flop element. 
     
     
       13. The method of claim 1, wherein the data path is an address path. 
     
     
       14. The method of claim 1, wherein in the test mode the integrated circuit device is tested at a super voltage above a normal operating voltage of the integrated circuit device. 
     
     
       15. The method of claim 14, wherein the data path is tested in both a first logic state and a second logic state of a clock signal at the super voltage. 
     
     
       16. The method of claim 1, wherein the integrated circuit device is a synchronous clocked device. 
     
     
       17. The method of claim 1, wherein conduction of the master element and conduction of the slave element initializes an address path of the integrated circuit device such that a plurality of columns and a plurality of rows of the integrated circuit device are not selected. 
     
     
       18. The method of claim 1, wherein conduction of the master element and conduction of the slave element initializes an address path of the integrated circuit device such that a plurality of columns and a plurality of rows of the integrated circuit device are selected. 
     
     
       19. The method of claim 18, wherein when the address path of the integrated circuit device is initialized, a plurality of bitlines true of the integrated circuit device are held at a first voltage level and a plurality of bitlines complement of the integrated circuit device are held at a second voltage level. 
     
     
       20. Circuitry for initializing a data path of a synchronous integrated circuit device, comprising: a clock control circuitry, having a first clock signal as an input signal and a test mode signal as an input signal and generating a second clock signal, which causes a master element of the integrated circuit device to conduct as a function of the first clock signal; and   a slave element of the integrated circuit device which is caused to conduct as a function of the second clock signal generated by the clock control circuitry;   wherein when the test mode signal is equal to a first logic state, the integrated circuit device is in a normal operating mode during which the master element conducts and wherein when the test mode signal is equal to a second logic state, the integrated circuit device is in a test mode during which the master element and the slave element conduct simultaneously.   
     
     
       21. The circuitry of claim 20, wherein the clock control circuitry for controlling the second clock signal to cause conduction of the slave element of the synchronous integrated circuit device comprises: a first transistor element, having a first terminal connected to a first supply voltage;   a second transistor element, having a first terminal connected to a second terminal of the first transistor element and a control element controlled by the first clock signal;   a third transistor element, having a first terminal connected to a second terminal of the second transistor element, a second terminal connected to a second supply voltage and a control terminal controlled by the first clock signal;   a fourth transistor element, having a first terminal connected to the first terminal of the third transistor element to produce the second clock signal of the clock control circuitry and a second terminal connected to the second supply voltage; and   a logic gate, having a control signal as an input signal and producing an output signal which controls a control terminal of the first transistor element and a control terminal of the fourth transistor element;   wherein the second clock signal can be forced to a logic state regardless of the first clock signal.   
     
     
       22. The circuitry of claim 21, wherein the control signal is a derivative signal of the test mode signal of the synchronous integrated circuit device. 
     
     
       23. The circuitry of claim 21, wherein the first transistor element is a p-channel transistor, the second transistor element is a p-channel transistor, the third transistor element is an n-channel transistor and the fourth transistor element is an n-channel transistor. 
     
     
       24. The circuitry of claim 21, wherein the first clock signal is a clock signal external to the synchronous integrated circuit device. 
     
     
       25. The circuitry of claim 21, wherein a power-on-reset signal is an input signal of the logic gate. 
     
     
       26. The circuitry of claim 25, wherein the second clock signal can be forced to the logic state as a function of the control signal and the power-on-reset signal. 
     
     
       27. The circuitry of claim 21, wherein the first supply voltage is Vcc and the second supply voltage is Vss. 
     
     
       28. The circuitry of claim 21, wherein the logic gate is a NAND logic gate. 
     
     
       29. The circuitry of claim 21, wherein the data path is an address path. 
     
     
       30. The circuitry of claim 21, wherein in the test mode the integrated circuit device is tested at a super voltage above a normal operating voltage of the integrated circuit device. 
     
     
       31. The circuitry of claim 21, wherein the data path is tested in both a first logic state and a second logic state of a clock signal at the super voltage. 
     
     
       32. The circuitry of claim 20, wherein the synchronous integrated circuit device is a synchronous clocked device. 
     
     
       33. The circuitry of claim 21, wherein conduction of the master element and conduction of the slave element initializes an address path of the integrated circuit device such that a plurality of columns and a plurality of rows of the integrated circuit device are not selected. 
     
     
       34. The circuitry of claim 21, wherein conduction of the master element and conduction of the slave element initializes an address path of the integrated circuit device such that a plurality of columns and a plurality of rows of the integrated circuit device are selected. 
     
     
       35. The circuitry of claim 34, wherein when the address path of the integrated circuit device is initialized, a plurality of bitlines true of the integrated circuit device are held at a first voltage level and a plurality of bitlines complement of the integrated circuit device are held at a second voltage level. 
     
     
       36. The circuitry of claim 21, wherein the master element and the slave element conduct simultaneously to initialize the data path of the integrated circuit device upon power-up of the integrated circuit device in the test mode. 
     
     
       37. The circuitry of claim 36, wherein the master element and the slave element conduct simultaneously for the duration of the test mode. 
     
     
       38. The circuitry of claim 21, wherein the test mode is entered upon power-up of the synchronous integrated circuit device. 
     
     
       39. The circuitry of claim 21, wherein the first clock signal is initialized internal to the synchronous integrated circuit device. 
     
     
       40. The circuitry of claim 21, wherein the second clock signal is controlled to cause conduction of the slave latch element regardless of a logic state of the first clock. 
     
     
       41. The circuitry of claim 40, wherein the second clock signal is controlled to cause conduction of the slave latch element by the clock control circuitry. 
     
     
       42. The circuitry of claim 21, wherein the first clock signal is a master clock signal and the second clock signal is a derivative signal of the master clock signal. 
     
     
       43. The circuitry of claim 42, wherein the master clock signal is a signal external to the synchronous integrated circuit device. 
     
     
       44. The circuitry of claim 21, wherein the master element is a master latch element and the slave element is a slave latch element. 
     
     
       45. The circuitry of claim 21, wherein the master element is a master flip-flop element and the slave element is a slave flip-flop element.