Dynamic random access memory having sequential word line refresh

Abstract

A DRAM includes a refresh controller including a clock control section for producing a refresh mode signal in response to an external control clock signal, a refresh logic section for producing an enable signal in response to the refresh mode signal, a refresh counter for sequentially producing a first plurality of row address signals during an active period of a row address strobe signal in response to the enable signal, a row address buffer for producing a second plurality of row address signals in response to the row address signals, and a row decoder including a plurality of word line drivers which sequentially decode the second plurality of row address signals provided from the row address buffer and sequentially enables word lines corresponding to the decoded row address signals.

That which is claimed: 
     
       1. A dynamic random access memory (DRAM), comprising: clock control means for producing a refresh mode signal in response to an external control clock signal, said external clock control signal including a row address strobe signal having an active period;   refresh logic means, responsive to said clock control means, for producing an enable signal in response to said refresh mode signal provided from said clock control means;   refresh counter means, responsive to said refresh logic means, for sequentially producing a first plurality of row address signals during one active period of said row address strobe signal in response to said enable signal provided from said refresh logic means;   a row address buffer, responsive to said refresh counter means, for producing a second plurality of row address signals during said one active period of said row address strobe signal in response to said first plurality of row address signals provided from said refresh counter means; and   a row decoder, responsive to said row address buffer including a plurality of word line drivers which sequentially decode said second plurality of row address signals provided from said row address buffer to produce a decoded second plurality of row address signals and to sequentially enable a plurality of word lines corresponding to the decoded second plurality of row address signals, during said one active period of said row address strobe signal.   
     
     
       2. A DRAM according to claim 1, wherein said refresh logic means comprises a timer which is enabled in response to said refresh mode signal and produces a plurality of clock signals during said one active period of said row address strobe signal. 
     
     
       3. A DRAM according to claim 1, wherein said refresh counter means comprises counters which are enabled in response to said refresh mode signal and receive and count said enable signal provided from said refresh logic means.