Method and apparatus for handling multiplexer contention during scan

Abstract

A method and apparatus for handling multiplexer contention during scan. During a test scan of a multiplexer circuit, it is possible for multiple inputs of a multiplexer to be selected at the same time in what is referred to as multiplexer contention. If the selected inputs are of different logical values, this contention may result in high power consumption and damage to the circuit. The invention prevents the adverse consequences of multiplexer contention by disabling one direction of the driving capability for each driving gate in the multiplexer during a scan. Thus, the multiplexer output can be driven to only one logical value regardless of the logical values of the selected inputs. A controllable impedance element, such as a transistor, is coupled between an input driving gate of a multiplexer circuit and a voltage supply node. The impedance element is responsive to a scan control signal, such that the impedance element is disabled, i.e., at high impedance, during a scan procedure. The input driving gate is therefore prevented from driving the multiplexer output towards the potential of the voltage supply node during a scan procedure. During normal operation, the impedance element is enabled, i.e., at low impedance, and the input driving gate is substantially unaffected.

We claim: 
     
       1. A multiplexer circuit comprising: an input driving gate selectively coupled to an output node; and   a controllable impedance element coupled between said input driving gate and a voltage supply node, wherein said controllable impedance element is disabled in response to a scan control signal.   
     
     
       2. The multiplexer circuit of claim 1 wherein said voltage supply node is a lower voltage supply. 
     
     
       3. The multiplexer circuit of claim 2 wherein said controllable impedance element is an NMOS transistor. 
     
     
       4. The multiplexer circuit of claim 1 wherein said voltage supply node is an upper voltage supply. 
     
     
       5. The multiplexer circuit of claim 4 wherein said controllable impedance element is a PMOS transistor. 
     
     
       6. The multiplexer circuit of claim 1 further comprising: a second input driving gate selectively coupled to said output node, wherein said controllable impedance element is further coupled between said second input driving gate and said voltage supply node.   
     
     
       7. The multiplexer circuit of claim 1 further comprising: a second input driving gate selectively coupled to said output node; and   a second controllable impedance element coupled between said second input driving gate and said voltage supply node, wherein said second controllable impedance element is responsive to said scan control signal.   
     
     
       8. The multiplexer circuit of claim 1 further comprising: a latch circuit coupled to said output node.   
     
     
       9. The multiplexer circuit of claim 1 further comprising: a third controllable impedance element coupled between said output node and a second voltage supply node, wherein said third controllable impedance element is responsive to said scan control signal.   
     
     
       10. The multiplexer circuit of claim 1 further comprising: a transmission gate coupled between said first input driving gate and said output node, said transmission gate responsive to a select signal.   
     
     
       11. The multiplexer circuit of claim 10 further comprising: a scan register coupled to said transmission gate to provide said select signal.   
     
     
       12. A method of handling multiplexer contention during scan, comprising the steps of: during a scan procedure, forming a high impedance between an input driving gate of a multiplexer and a voltage supply node; and   during normal circuit operation, forming a low impedance between said input driving gate and said voltage supply node.   
     
     
       13. The method of claim 12 wherein said step of forming a high impedance further comprises the step of: disabling a transistor coupled between said driving gate and said voltage supply node.   
     
     
       14. The method of claim 12 wherein said step of forming a low impedance further comprises the step of: enabling a transistor coupled between said driving gate and said voltage supply node.   
     
     
       15. The method of claim 12 further comprising the step of: asserting a scan control signal during said scan procedure.   
     
     
       16. The method of claim 12 further comprising the step of: forming a low impedance between an output node of said multiplexer and a second voltage supply node during said scan procedure.   
     
     
       17. The method of claim 12 further comprising the step of: latching a signal value at an output node of said multiplexer.   
     
     
       18. A computer system comprising: an integrated circuit having a test scan configuration comprising a plurality of scan registers coupled to combinational logic circuitry, wherein said combinational logic circuitry further comprises: a multiplexer circuit having an input driving gate selectively coupled to an output node; and   a controllable impedance element coupled between said input driving gate and a voltage supply node, wherein said controllable impedance element is disabled in response to a scan control signal.     
     
     
       19. The computer system of claim 18 wherein said voltage supply node is a lower voltage supply. 
     
     
       20. The computer system of claim 19 wherein said controllable impedance element is an NMOS transistor. 
     
     
       21. The computer system of claim 18 wherein said voltage supply node is an upper voltage supply. 
     
     
       22. The computer system of claim 21 wherein said controllable impedance element is a PMOS device. 
     
     
       23. The computer system of claim 18 wherein said multiplexer circuit further comprises: a second input driving gate selectively coupled to said output node, wherein said controllable impedance element is further coupled between said second input driving gate and said voltage supply node.   
     
     
       24. The computer system of claim 18 wherein said combinational logic circuitry further comprises: a second input driving gate selectively coupled to said output node; and   a second controllable impedance element coupled between said second input driving gate and said voltage supply node, wherein said second controllable impedance element is responsive to said scan control signal.   
     
     
       25. The computer system of claim 18 wherein said combinational logic circuitry further comprises: a latch circuit coupled to said output node.   
     
     
       26. The computer system of claim 18 wherein said combinational logic circuitry further comprises: a third controllable impedance element coupled between said output node and a second voltage supply node, wherein said third controllable impedance element is responsive to said scan control signal.   
     
     
       27. The computer system of claim 18 wherein said multiplexer circuit further comprises: a transmission gate coupled between said first input driving gate and said output node, said transmission gate responsive to a select signal from a scan register.