Circuit for coupling an event indication signal across asynchronous time domains

Abstract

A circuit is for re-synchronizing an event indication signal received from a foreign domain to generate a result indication signal that is re-synchronized to a host clock signal. The event indication signal is received from the foreign domain at a first input terminal; and a host clock signal is received at a second input terminal. Edge-triggered flip flop circuitry of the circuit has a clock input, a data input, and a data output. The clock input is coupled to the second input terminal and the data input is coupled to receive a latch output signal. The edge-triggered flip flop circuitry clocks the latch output signal to the data output of the flip flop circuitry, to generate a result event indication signal, in response to a transition in the host clock signal. Delay circuitry is coupled to the first input terminal to receive the event indication signal. The delay circuitry provides a delayed event indication signal having a phase that is delayed from the event indication signal. Transparent latch circuitry latches the delayed event indication signal responsive to a latch control signal, and combination circuitry is coupled to receive the event indication signal and the result event indication signal, and provides a combination thereof as the latch control signal.

What is claimed is: 
     
       1. A circuit for re-synchronizing an event indication signal received from a foreign domain, to generate a result indication signal that is re-synchronized to a host clock signal, the circuit comprising: a first input terminal to receive the event indication signal from foreign domain;   a second input terminal to receive the host clock signal;   an output terminal;   edge-triggered flip flop circuitry, having a clock input, a data input, and a data output, the clock input coupled to the second input terminal the data input coupled to receive a latch output signal, that clocks the latch output signal to the data output of the flip flop circuitry, to generate a result event indication signal at the output terminal, in response to a transition the host clock signal;   delay circuitry coupled to the first input terminal to receive the event indication signal, that provides a delayed event indication signal having a phase that is delayed from the event indication signal;   transparent latch circuitry that latches the delayed event indication signal responsive to a latch control signal for providing said latch output signal; and   combination circuitry coupled to receive the event indication signal and the result event indication signal and that provides a combination thereof as the latch control signal.   
     
     
       2. The circuit of claim 1, and further including: inverter circuitry at the first input terminal that inverts the event indication signal to generate an inverted event indication signal and that provides the inverted event indication signal as the event indication signal.   
     
     
       3. The circuit of claim 1 or 2, wherein the combination circuitry has a first data input, a second data input and a data output, the first input coupled to receive the event indication signal and the second input coupled to receive the result event indication signal, wherein the combination circuitry provides, at the data output of the combination circuitry, a NAND function of the event indication signal and an inverted signal of the result event indication signal as the latch control signal. 
     
     
       4. The circuit of claim 1 or 2, wherein the delay circuitry includes a plurality of buffer circuits and a plurality of inverter circuits, connected in serial. 
     
     
       5. The circuit of claim 1 or 2, wherein the edge-triggered flip flop circuitry is first edge-triggered flip-flop circuitry, and further including: second edge-triggered flip flop circuitry, having a clock input, a data input and a data output, the clock input coupled to the second input terminal and the data input coupled to the data output of the first edge-triggered flip-flop circuitry, wherein a metastability-proofed result event indication signal is provided at the data output of the second edge-triggered flip-flop circuitry.   
     
     
       6. The circuit of claim 1, and further including: enablable inverter circuitry coupled to the first input terminal and responsive to a polarity control signal, that provides to the delay circuitry and the combination circuitry,   the event indication signal when the polarity control signal has a first polarity: and   an inverted signal of the event indication signal when the polarity control signal has a second polarity.   
     
     
       7. The circuit of claim 6, wherein the enablable inverter circuitry is XOR circuitry that provides the event indication signal to the delay circuitry and the combination circuitry when the polarity control signal has a first state, and   provides the event indication signal, inverted, to the delay circuitry and the combination circuitry when the polarity signal has a second state, opposite the first state.   
     
     
       8. The circuit of claim 7, wherein the polarity control signal in the first state has a low level and the polarity signal in the second state has a high level.