Fault tolerant sync mark detector enabled relative to a frequency of an acquisition preamble for sampled amplitude recording

Abstract

A sampled amplitude read channel reads data from a magnetic medium by detecting digital data from a sequence of discrete time sample values generated by sampling an analog read signal from a read head positioned over the magnetic medium. The digital data comprises a preamble field followed by a sync mark followed by a data field. Timing recovery in the read channel synchronizes to a phase and frequency of the preamble field and a sync detector detects the sync mark in order to frame operation of an RLL decoder for decoding the detected data field. To decrease the probability of early misdetection, the sync mark is chosen to have minimum correlation with shifted versions of the sync mark concatenated with the preamble field. To further increase the fault tolerance, the sync mark detector is enabled by timing recovery relative to the end of the preamble field. A state machine in timing recovery generates expected sample values used to acquire the preamble field, and a current state of the state machine indicates when the preamble ends relative to a predetermined clock interval. In this manner, the search for an appropriate sync mark need only look for minimum correlation during shifts at the predetermined clock interval, thereby increasing the fault tolerant characteristic of the sync mark.

We claim: 
     
       1. A fault tolerant sync mark detector in a sampled amplitude read channel for reading data from a magnetic disc medium by detecting digital data from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic disc medium, wherein: the read channel generates channel values in response to the sample values; and   the magnetic disc medium comprises a preamble field recorded at a predetermined frequency;   the sync mark detector comprising: (a) a comparator for comparing the channel values to a target sync mark; and   (b) an input for receiving a sample period interval control signal for enabling operation of the sync mark detector relative to the frequency of the preamble.     
     
     
       2. The fault tolerant sync mark detector as recited in claim 1, wherein the channel values are the digital data. 
     
     
       3. The fault tolerant sync mark detector as recited in claim 1, wherein the channel values are estimated sample values. 
     
     
       4. The fault tolerant sync mark detector as recited in claim 1, wherein a length and a value of the target sync mark are programmable. 
     
     
       5. The fault tolerant sync mark detector as recited in claim 1, wherein the comparator comprises a correlator comprising: (a) a storage register for storing the target sync mark;   (b) a shift register shifted at a predetermined clock rate for storing the channel values; and   (c) a means for correlating the storage register with the shift register to generate an output, wherein the output is enabled by control signal at a predetermined clock rate interval relative to the frequency of the preamble.   
     
     
       6. The fault tolerant sync mark detector as recited in claim 5, wherein the predetermined clock rate interval is two clock cycles. 
     
     
       7. The fault tolerant sync mark detector as recited in claim 5, wherein: (a) the control signal is generated by a timing recovery circuit that acquires a phase and frequency of the preamble field during an acquisition mode; and   (b) the timing recovery circuit generates expected sample values X(n) used to acquire the preamble field during the acquisition mode.   
     
     
       8. The fault tolerant sync mark detector as recited in claim 7, wherein: (a) the expected sample values are generated by a state machine; and   (b) a current state of the state machine generates the control signal.   
     
     
       9. The fault tolerant sync mark detector as recited in claim 8, wherein the state machine is a counter. 
     
     
       10. The fault tolerant sync mark detector as recited in claim 1, wherein the sync mark detector comprises a programmable threshold detector for detecting when a result of the comparison exceeds a predetermined value. 
     
     
       11. The fault tolerant sync mark detector as recited in claim 1, wherein: (a) the digital data comprises: user data comprising a user preamble field followed by a user sync mark followed by a user data field; and embedded servo data comprising a servo preamble field followed by a servo sync mark followed by a servo data field;   (b) the fault tolerant sync mark detector is programmed to detect the user sync mark when the read channel is detecting the user data; and   (c) the fault tolerant sync mark detector is programmed to detect the servo sync mark when the read channel is detecting the servo data.   
     
     
       12. The fault tolerant sync mark detector as recited in claim 1, wherein the sync mark detector processes an even and odd interleave of the channel values in parallel. 
     
     
       13. A fault tolerant method of detecting a sync mark in a sampled amplitude read channel for reading data from a magnetic disc medium by detecting digital data from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic disc medium, comprising the steps of: (a) acquiring a preamble field recorded on the magnetic disc medium at a predetermined frequency;   (b) generating channel values in response to the sample values; and   (c) directly comparing the channel values to a target sync mark according to a predetermined sample period interval relative to the frequency of the preamble.   
     
     
       14. The fault tolerant method of detecting a sync mark as recited in claim 13, wherein the channel values are the digital data. 
     
     
       15. The fault tolerant method of detecting a sync mark as recited in claim 13, wherein the channel values are estimated sample values. 
     
     
       16. The fault tolerant method of detecting a sync mark as recited in claim 13, wherein a length and a value of the target sync mark is programmable. 
     
     
       17. The fault tolerant method of detecting a sync mark as recited in claim 13, further comprising the steps of: (a) storing the target sync mark in a storage register;   (b) shifting the channel values into a shift register at a predetermined clock rate; and   (c) correlating the storage register with the shift register to generate an output; and   (d) enabling the output at a predetermined clock rate interval relative to the frequency of the preamble.   
     
     
       18. The fault tolerant method of detecting a sync mark as recited in claim 17, wherein the predetermined clock rate interval is two clock cycles. 
     
     
       19. The fault tolerant method of detecting a sync mark as recited in claim 17, further comprising the steps of: (a) acquiring a phase and frequency of the preamble field during an acquisitions mode; and   (b) generating expected sample values X(n) used to acquire the preamble field during the acquisition mode.   
     
     
       20. The fault tolerant method of detecting a sync mark as recited in claim 19, further comprising the steps of: (a) generating the expected sample values with a state machine; and   (b) enabling the output according to a current state of the state machine.   
     
     
       21. The fault tolerant method of detecting a sync mark as recited in claim 20, wherein the state machine is a counter. 
     
     
       22. The fault tolerant method of detecting a sync mark as recited in claim 13, further comprising the step of detecting when a result of the comparison exceeds a predetermined value. 
     
     
       23. The fault tolerant method of detecting a sync mark as recited in claim 13, wherein the digital data comprises user data comprising a user preamble field followed by a user sync mark followed by a user data field and embedded servo data comprising a servo preamble field followed by a servo sync mark followed by a servo data field; further comprising the steps of: (a) detecting the user sync mark using a user target sync mark when the read channel is detecting the user data; and   (b) detecting the servo sync mark using a servo target sync mark when the read channel is detecting the servo data.   
     
     
       24. The fault tolerant method of detecting a sync mark as recited in claim 13, further comprising the step of processing an even and odd interleave of the channel values in parallel. 
     
     
       25. A sampled amplitude read channel for reading data from a magnetic disc medium by detecting digital data from a sequence of discrete time sample values generated by sampling pulses in an analog read signal from a magnetic read head positioned over the magnetic disc medium, the digital data comprises a preamble field followed by a sync mark followed by a data field, the sampled amplitude read channel comprising: (a) a timing recovery circuit for acquiring a phase and frequency of the preamble field and outputting a control signal in response to the preamble field;   (b) a detector for detecting an estimated data sequence from the discrete time sample values; and   (c) a fault tolerant sync mark detector, directly responsive to the control signal and the estimated data sequence, for detecting a sync mark in the estimated data sequence and framing operation of an RLL decoder.