Space efficient column decoder for flash memory redundant columns

Abstract

The present invention is a space efficient redundant column decoder circuit for use in a non-volatile memory device. The redundant column decoder compares a n-bit stored defective address with a n-bit presented address. Based on this comparison, an output signal is generated. This output signal is used both to specify the redundant column (or set of columns) associated with the redundant column decoder circuit, and to de-activate all of the other column decoders in the device. The redundant column decoder has a pull-up path and a parallel combination of n pairs of complementary pull-down paths. The pull-up path is connected to the pull-down paths at an output node, and the output signal is taken at this output node. Each pair of complementary pull-down paths has a first pull-down path and a second pull-down path. The first pull down path has a first non-volatile memory cell in series with and connected to a first address transistor. The first address transistor is also connected to the output node. The second pull-down path has a second non-volatile memory cell in series with and connected to a second address transistor. The second address transistor is also connected to the output node. At least one of the pull-down paths is conductive when the stored defective address does not match the presented address. Conversely, all of the pull-down paths are non-conductive when the stored defective address matches the presented address.

What is claimed is: 
     
       1. A redundant column decoder circuit for comparing a n-bit stored defective address with a n-bit presented address and generating an output signal, said circuit comprising: a pull-up path, and   a parallel combination of n pairs of complementary pull-down paths, connected to said pull-up path at an output node, said output signal being taken at said output node,   wherein each of said pair of pull-down paths comprises, a first pull-down path comprising a first non-volatile memory cell in series with and connected to a first address transistor, said first address transistor further connected to said output node, and   a second pull-down path comprising a second non-volatile memory cell in series with and connected to a second address transistor, said second address transistor further connected with said output node,     wherein at least one of said pull-down paths is conductive when said stored defective address does not match said presented address, and all of said pull-down paths are non-conductive when said stored defective address matches said presented address.   
     
     
       2. A circuit according to claim 1 wherein the gate of said first address transistor is connected to an address signal representing one bit of said presented column address,   the gate of said second address transistor is connected to a signal which represents the logical negation of said address signal, and   said first non-volatile memory cell is in a complementary state to said second non-volatile memory cell when said redundant column decoder circuit is comparing said stored defective column address and said presented column address.   
     
     
       3. A circuit according to claim 2 wherein said first pull down-path further comprises a first access transistor in series with and connected to said non-volatile memory cell, and said second pull-down path further comprises a second access transistor in series with and connected to said second non volatile memory cell. 
     
     
       4. A redundant column decoder circuit for comparing a n-bit column address with a n-bit presented address and generating an output signal, said circuit comprising: n parallel address bit comparison circuits, each address bit comparison circuit including: a pair of non-volatile memory cells, including a first non-volatile memory cell for storing one respective bit of said n-bit column address and a second non-volatile memory cell for storing said one bit's boolean negation; and   a pair of transistors, wherein each transistor in said pair of transistors is connected in series with a respective non-volatile memory cell in said pair of non-volatile memory cells, said pair of transistors having a first transistor whose gate is coupled to a respective presented address bit signal representing a respective bit of said n-bit presented address and a second transistor whose gate is coupled to a signal comprising the boolean negation of said signal coupled to the gate of said one first transistor;     each address bit comparison circuit forming two parallel current paths; and   a summing circuit node coupled to the parallel current paths in all of said n parallel address bit comparison circuits, such that when said n-bit address does not match said presented address said summing circuit node is driven to a first signal state and when said n-bit address does match said presented address said summing circuit node is driven to a second signal state that is the boolean negation of said first signal state.   
     
     
       5. A circuit according to claim 4 wherein each address bit comparison circuit further includes two access transistors, each connected in series with a respective one of said non-volatile memory cells, said access transistors providing access to said non-volatile memory cells for programming thereof and providing a current path during address decoding.