Voltage control type delay circuit and internal clock generation circuit using the same

Abstract

A control transistor is connected in parallel with an input transistor of a bias generation circuit in a voltage control delay circuit. A power supply potential Vcc is divided by voltage divider resistors to be applied to the gate of the control transistor. Reduction in the power supply potential Vcc causes reduction in a current Ib flowing to the control transistor, and a current Ic=Ia+Ib flowing to a delay time variable element. When the power supply potential Vcc is reduced, the factor of a delay time period of delay time variable elements becoming shorter due to a smaller amplitude of a clock signal is canceled with the factor of the delay time period of the delay time variable elements become longer due to a smaller current Ic flowing thereto. Therefore, variation in the delay time period can be suppressed to a low level.

What is claimed is: 
     
       1. A voltage control type delay circuit for delaying an input signal by a time period according to a control voltage and providing the delayed signal, said voltage control type delay circuit comprising: a first transistor connected in series between a node and a first power supply potential line, for receiving said control voltage for conducting a current of a value according to the control voltage,   a second transistor connected in series between said node and a second power supply potential line,   a current control circuit connected to said node for increasing or decreasing a current flowing to said second transistor by a value according to a change in a power supply voltage, and   a delay circuit for delaying said input signal by a time period according to said current flowing to said second transistor and providing the delayed signal, wherein said current control circuit comprises: a third transistor connected in parallel with said first transistor for distributing a current flowing to said second transistor, and   a voltage-down circuit for down-converting said power supply voltage and supplying the down-converted voltage to said third transistor.     
     
     
       2. The voltage control type delay circuit according to claim 1, wherein said voltage-down circuit comprises: a first voltage divider resistor connected between an input electrode of said third transistor and said second power supply potential line, and   a second voltage divider resistor connected between the input electrode of said third transistor and said first power supply potential line.   
     
     
       3. The voltage control type delay circuit according to claim 2, wherein said delay circuit comprises a plurality of delay time variable elements connected in series, each having a delay time period varied according to the current flowing to said second transistor. 
     
     
       4. A voltage control type delay circuit for delaying an input signal by a time period according to a control voltage and providing the delayed signal, said voltage control type delay circuit comprising: a first transistor connected in series between a node and a first power supply potential line, for receiving said control voltage for conducting a current of a value according to the control voltage,   a second transistor connected in series between said node and a second power supply potential line,   a current control circuit connected to said node for increasing or decreasing a current flowing to said second transistor by a value according to a change in a power supply voltage, and   a delay circuit for delaying said input signal by a time period according to said current flowing to said second transistor and providing the delayed signal, wherein said current control circuit comprises: a third transistor connected in parallel with said second transistor for distributing a current flowing to said first transistor, and a voltage-down circuit for down-converting said power supply voltage and supplying the down-converted voltage to said third transistor.     
     
     
       5. The voltage control type delay circuit according to claim 4, wherein said voltage-down circuit comprises: a first voltage divider resistor connected between an input electrode of said third transistor and said second power supply potential line and   a second voltage divider resistor connected between the input electrode of said third transistor and said first power supply potential line.   
     
     
       6. The voltage control type delay circuit according to claim 5, wherein said delay circuit comprises a plurality of delay time variable elements connected in series, each having a delay time period varied according to said current flowing to said second transistor. 
     
     
       7. A voltage control type delay circuit for delaying an input signal by a time period according to a control voltage and providing the delayed signal, said voltage control type delay circuit comprising: a first conductivity type first transistor connected between a first node and a ground potential line, for receiving said control voltage for conducting a current of a value corresponding to said control voltage;   a second conductivity type second transistor connected between said first node and a power supply potential line, having its input electrode connected to said first node;   a second conductivity type third transistor connected between a second node and said power supply potential line, and having its input electrode connected to said first node;   a first conductivity type fourth transistor connected between said second node and said ground potential line, and having its input electrode connected to said second node;   a current control circuit connected to said first node for increasing or decreasing current flowing to said second transistor by a value according to a change in a power supply voltage; and   a delay circuit including a plurality of delay time variable elements connected in series for delaying said input signal by a time period according to current flowing to said third and fourth transistors and providing the delayed signal, wherein said current control circuit comprises a first conductivity type fifth transistor connected between said first node and said ground potential line, and   a voltage-down circuit for down-converting said power supply voltage and supplying the down-converted voltage to said fifth transistor.     
     
     
       8. The voltage control type delay circuit according to claim 7, wherein said voltage-down circuit comprises a first voltage divider resistor connected between an input electrode of said fifth transistor and said power supply potential line, and   a second voltage divider resistor connected between the input electrode of said fifth transistor and said ground potential line.   
     
     
       9. The voltage control type delay circuit according to claim 8, wherein each of said plurality of delay time variable elements of said delay circuit comprises an input node for receiving said input signal from a delay time variable element of a preceding stage,   an output node for providing said input signal to a delay time variable element of a succeeding stage,   first conductivity type sixth and seventh transistors connected in series between said output node and said ground potential line, having one input electrode connected to said input node and another input electrode connected to said second node, and   second conductivity type eighth and ninth transistors connected in series between said output node and said power supply potential line, having one input electrode connected to said input node and another input electrode connected to said first node.   
     
     
       10. A voltage control type delay circuit for delaying an input signal by a time period according to a control voltage and providing the delayed signal, said voltage control type delay circuit comprising: a first conductivity type first transistor connected between a first node and a ground potential line, for receiving said control voltage for conducting a current of a value corresponding to said control voltage;   a second conductivity type second transistor connected between said first node and a power supply potential line, having its input electrode connected to said first node;   a second conductivity type third transistor connected between a second node and said power supply potential line, and having its input electrode connected to said first node;   a first conductivity type fourth transistor connected between said second node and said ground potential line, and having its input electrode connected to said second node;   a current control circuit connected to said first node for increasing or decreasing current flowing to said second transistor by a value according to a change in a power supply voltage; and   a delay circuit including a plurality of delay time variable elements connected in series for delaying said input signal by a time period according to current flowing to said third and fourth transistors and providing the delayed signal, wherein said current control circuit comprises a second conductivity type fifth transistor connected between said first node and said power supply potential line, and   a voltage-down circuit for down-converting said power supply voltage and supplying the down-converted voltage to said fifth transistor.     
     
     
       11. The voltage control type delay circuit according to claim 10, wherein said voltage-down circuit comprises: a first voltage divider resistor connected between an input electrode of said fifth transistor and said power supply potential line, and   a second voltage divider resistor connected between the input electrode of said fifth transistor and said ground potential line.   
     
     
       12. The voltage control type delay circuit according to claim 11, wherein each of said plurality of delay time variable elements of said delay circuit comprises an input node for receiving said input signal from a delay time variable element of a preceding stage,   an output node for providing said input signal to a delay time variable element of a succeeding stage,   first conductivity type sixth and seventh transistors connected in series between said output node and said ground potential line, having one input electrode connected to said input node and another input electrode connected to said second node, and   second conductivity type eighth and ninth transistors connected in series between said output node and said power supply potential line, having one input electrode connected to said input node and another input electrode connected to said first node.   
     
     
       13. An internal clock generation circuit for generating an internal clock signal in synchronization with an external clock signal, said internal clock generation circuit comprising: a control voltage generation circuit receiving said external clock signal and said internal clock signal for providing a control voltage according to a phase difference between said two clock signals,   a first transistor receiving said control voltage for conducting a current of a value according to the control voltage,   a second transistor connected in series with said first transistor,   a current control circuit connected to a node between said first and second transistors for increasing or decreasing a current flowing to said second transistor by a value according to a change in a power supply voltage, and   a delay circuit for delaying said external clock signal by a time period according to said current flowing to said second transistor and providing the delayed signal as said internal clock signal, wherein said current control circuit comprises: a third transistor connected in parallel with said first transistor for distributing a current flowing to said second transistor, and   a voltage-down circuit for down-converting said power supply voltage and supplying the down-converted voltage to said third transistor.     
     
     
       14. An internal clock generation circuit for generating an internal clock signal in synchronization with an external clock signal, said internal clock generation circuit comprising: a control voltage generation circuit receiving said external clock signal and said internal clock signal for providing a control voltage according to a phase difference between said two clock signals,   a first conductivity type first transistor connected between a first node and a ground potential line, receiving said control voltage for conducting a current of a value according to said control voltage,   a second conductivity type second transistor connected between said first node and a power supply potential line, having its input electrode connected to said first node,   a second conductivity type third transistor connected between a second node and said power supply potential line, having its input electrode connected to said first node,   a first conductivity type fourth transistor connected between said second node and said ground potential line, having its input electrode connected to said second node,   a current control circuit connected to said first node for increasing or decreasing a current flowing to said second transistor by a value according to a change in a power supply voltage, and   a delay circuit including a plurality of delay time variable elements connected in series, for delaying said external clock signal by a time period according to said current flowing to said third and fourth transistors, and providing the delayed signal as said internal clock signal, wherein said current control circuit comprises a first conductivity type fifth transistor connected between said first node and said ground potential line, and   a voltage-down circuit for down-converting said power supply voltage and supplying the down-converted voltage to said fifth transistor.     
     
     
       15. A synchronous type semiconductor memory device generating an internal clock signal to operate in synchronization with an external clock signal, comprising: a memory array including a plurality of memory cells arranged in a matrix;   a control voltage generation circuit receiving said external clock signal and said internal clock signal for providing a control voltage according to a phase difference between said two clock signals;   a first transistor receiving said control voltage for conducting a current of a value according to the control voltage;   a second transistor connected in series with said first transistor;   a current control circuit connected to a node between said first and second transistors for increasing or decreasing a current flowing to said second transistor by a value according to a change in a power supply voltage;   a delay circuit for delaying said external clock signal by a time period according to said current flowing to said second transistor and providing the delayed signal as said internal clock signal; and   a data input/output circuit for inputting and outputting data signals in synchronization with said internal clock signal between selected memory cells of said memory array and an external output, wherein said current control circuit comprises: a third transistor connected in parallel with said first transistor for distributing a current flowing to said second transistor, and   a voltage-down circuit for down-converting said power supply voltage and supplying the down-converted voltage to said third transistor.     
     
     
       16. A synchronous type semiconductor memory device generating an internal clock signal to operate in synchronization with an external clock signal, comprising: a memory array including a plurality of memory cells arranged in a matrix;   a control voltage generation circuit receiving said external clock signal and said internal clock signal for providing a control voltage according to a phase difference between said two clock signals;   a first conductivity type first transistor connected between a first node and a ground potential line, receiving said control voltage for conducting a current of a value according to said control voltage;   a second conductivity type second transistor connected between said first node and a power supply potential line, having its input electrode connected to said first node;   a second conductivity type third transistor connected between a second node and said power supply potential line, having its input electrode connected to said first node;   a first conductivity type fourth transistor connected between said second node and said ground potential line, having its input electrode connected to said second node;   a current control circuit connected to said first node for increasing or decreasing a current flowing to said second transistor by a value according to a change in said power supply voltage;   a delay circuit including a plurality of delay time variable elements connected in series, for delaying said external clock signal by a time period according to said current flowing to said third and fourth transistors, and providing the delayed signal as said internal clock signal; and   a data input/output circuit for inputting and outputting data signals in synchronization with said internal clock signal between selected memory cells of said memory array and an external output, wherein said current control circuit comprises a first conductivity type fifth transistor connected between said first node and said ground potential line, and   a first voltage-down circuit for down-converting said power supply voltage and supplying the down-converted voltage to said fifth transistor.