Semiconductor device with increased on chip decoupling capacitance

Abstract

A semiconductor device has an on-board decoupling capacitor provided at its interconnect region. The decoupling capacitor comprises two layers of metallurgy separated by a dielectric layer wherein two of the layers are identically patterned.

We claim: 
     
       1. A method of forming a decoupling capacitor on a semiconductor device comprising the steps of: providing an insulating substrate having internal metallization layers with first and second lower levels of connection that provide electrical contacts at an upper surface of the insulating substrate electrically coupled to respective electrical lines of the internal metallization layers;   disposing over the first and second lower levels of connection at the upper surface of the insulating substrate at respective first and second regions thereof two layers of metallization co-aligned and separated by a dielectric layer, respective lower layers of the two layers of metallization of the first and second regions being electrically connected to the first and second lower levels of connection respectively of the insulating substrate through said electrical contacts coupled to said first and second lower levels of connection;   removing the dielectric layer and an upper layer of the two layers of metallization of the second region;   forming an insulating sidewall on a side of the first region facing the second region; and   depositing metallization on the substrate at a region including a part of both the first and second regions so as to electrically couple the upper layer of the first region to the remaining bottom layer of the second region.   
     
     
       2. A method according to claim 1 wherein said steps of disposing the two layers of metallization comprises: (a) depositing a first layer of metallization as a lower layer of metallization upon the substrate;   (b) depositing a dielectric material as a dielectric layer over the first layer of metallization;   (c) depositing a second layer of metallization as an upper layer of metallization over the dielectric layer; and   (d) providing a mask over the second layer of metallurgy, the mask having a predetermined pattern;   (e) etching exposed regions of the first and second layers of metallization and the dielectric layer in accordance with the predetermined pattern of said mask; and   (f) removing said mask and leaving the lower and upper layers of metallization separated by the dielectric layer and co-aligned in accordance with the predetermined pattern of said mask.   
     
     
       3. A method according to claim 1 wherein said step of removing comprises: forming a blocking mask over the first region of the two layers of metallization;   etching away the top layer of the two layers of metallization of the second region;   etching away the dielectric layer associated with the second region; and   removing said blocking mask.   
     
     
       4. A method of forming a decoupling capacitor on a semiconductor device comprising the steps of: providing an insulating substrate having an internal metallization layer with a stud that provides an electrical contact at an upper surface of the insulating substrate and is electrically coupled to the internal metallization layer;   disposing over the stud at the upper surface of the insulating substrate two layers of metallization co-aligned and separated by a dielectric layer while providing an opening through the dielectric layer and the two layers of metallization over the stud of the insulating substrate so as to leave the stud exposed at the upper surface of the insulating substrate;   forming insulating sidewalls around an interior periphery of said opening; and   depositing metallization over the substrate at a region encompassing the opening so as to electrically couple the stud to the top layer of the two layers of metallization.   
     
     
       5. A method according to claim 4 wherein said step of disposing the two layers of metallization comprises: providing a mask over the insulating substrate, the mask having a predetermined pattern;   depositing a first layer of metallization as the bottom layer of the two layers of metallization upon the substrate in accordance with the pattern of said mask;   depositing a dielectric material as the dielectric layer over the first layer of metallization in accordance with the pattern of said mask;   depositing a second layer of metallization as the upper layer of the two layers of metallization over the dielectric layer in accordance with the pattern of said mask; and   removing said mask and leaving the two layers of metallization separated by the dielectric layer and co-aligned in accordance with the predetermined pattern of said mask.   
     
     
       6. A method of forming a decoupling capacitor on a semiconductor device comprising the steps of: disposing over an insulating substrate upper and lower metallization layers of said capacitor, said metallization layers having at least two edges coaligned and being separated by a dielectric layer;   etching an opening through the dielectric layer and the upper metallization layer of said capacitor so to as to expose the lower metallization layer of said capacitor;   forming an insulation barrier on the side walls around an interior periphery of said opening and over the upper metallization layer of said capacitor around the periphery of said opening; and   depositing metallization over the substrate at a region encompassing the opening so as to provide an electrical contact to the lower metallization layer of said capacitor.   
     
     
       7. A method according to claim 6 wherein the step of forming the insulation barrier includes: depositing a passivation film over a region of the substrate including said opening;   forming a first mask over the substrate with an aperture therein encompassing an interior region of the opening in the upper metallization layer of said capacitor, the diameter across said aperture being less than the diameter across said opening of the upper metallization layer of said capacitor, said aperture providing exposure to the passivation film therebelow within said opening of the upper metallization layer of said capacitor;   etching exposed passivation through said first mask's aperture for a duration sufficient for removing exposed passivation film; and   removing said first mask.   
     
     
       8. A method according to claim 7 wherein said step of disposing said upper and lower layers of metallization comprises: providing a second mask over the insulating substrate, the second mask having a predetermined pattern;   depositing a first layer of metallization as the lower metallization layer of said capacitor upon the substrate in accordance with the pattern of said second mask;   depositing a dielectric material as the dielectric layer of said capacitor over the lower metallization layer of said capacitor in accordance with the pattern of said second mask;   depositing a second layer of metallization as the upper metallization layer of said capacitor over the dielectric layer in accordance with the pattern of said second mask; and   removing said second mask and leaving the upper and lower layers of metallization separated by the dielectric layer and co-aligned in accordance with the predetermined pattern of said second mask.