Low load host/PCI bus bridge

Abstract

A bridge for coupling a host bus to a peripheral component interconnect (PCI) bus. A controller is used to transfer an address from the host bus while a datapath is used to transfer data from the host bus. The address and data is then transferred to the PCI bus over a set of signal lines coupled to the PCI bus such that each signal line transfers at least a portion of the address as well as at least a portion of data.

What is claimed is: 
     
       1. A bridge for coupling a first bus operating at a first bus speed to a second bus operating at a second bus speed, said bridge comprising: a controller coupled to said first bus to transfer an address from said first bus;   a datapath coupled to said first bus to transfer data from said first bus; and   a plurality of signal lines coupled to said second bus, said second bus being capable of supporting only a finite number of loads, each signal line of said plurality of signal lines to transfer at least a portion of both said address and said data to said second bus, said plurality of signal lines contributing a first amount of load on said second bus that is less than a second amount of load that would be contributed on said second bus if each signal line of said plurality of signal lines were dedicated to transferring only said portion of said address.   
     
     
       2. The bridge of claim 1 wherein said datapath is coupled to said controller through a link, said datapath to transfer said data to said controller over said link at a datapath speed, said controller to transfer said address and said data over said plurality of signal lines to said second bus. 
     
     
       3. The bridge of claim 1 wherein said controller is coupled to said datapath through a link, said controller to transfer said address to said datapath over said link at a controller speed, said datapath to transfer said address and said data over said plurality of signal lines to said second bus. 
     
     
       4. The bridge of claim 1 further comprising a merger, said merger being coupled to said controller, said controller to transfer said address to said merger, said merger also being coupled to said datapath, said datapath to transfer said data to said merger, said merger to transfer said address and said data over said plurality of signal lines to said second bus. 
     
     
       5. The bridge of claim 2 wherein said datapath speed is faster than said second bus speed and the number of pins to transfer said data from said datapath to said controller within a finite period of time is less than the number of pins which would be required to transfer said data from said datapath to said second bus within an equivalent, finite period of time. 
     
     
       6. The bridge of claim 3 wherein said controller speed is faster than said second bus speed, and the number of pins to transfer said address to said datapath within a finite period of time is less than the number of pins which would be required to transfer said address from said controller to said second bus within an equivalent, finite period of time. 
     
     
       7. The bridge of claim 5 wherein approximately 16 pins are required to transfer said data to said controller from said datapath. 
     
     
       8. The bridge of claim 2 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       9. The bridge of claim 7 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       10. The bridge of claim 1, wherein the first bus operating at a first bus speed includes a host bus operating at a host bus speed and wherein the second bus operating at a second bus speed includes a Peripheral Component Interconnect (PCI) bus operating at a PCI bus speed. 
     
     
       11. A bridge for coupling a first bus operating at a first bus speed to a second bus operating at a second bus speed, said bridge comprising: a datapath coupled to said first bus at one end and a controller at another end, said datapath to transfer data from said first bus to said controller at a datapath speed, said datapath speed being approximately n times faster than said second bus speed, and the number of pins to transfer said data to said controller within a finite period of time is approximately 1/n times the number of pins which would be required to transfer said data to said second bus within an equivalent, finite period of time; and   said controller coupled to said first bus, said datapath, and said second bus, said controller to transfer an address from said first bus to said second bus, said controller also to transfer said data from said datapath to said second bus such that an additional load to said second bus is not required as a result of routing said data from said datapath through said controller rather than directly to said second bus.   
     
     
       12. The bridge of claim 11 wherein said datapath speed is approximately twice said second bus speed, and approximately 16 pins transfer said data from said datapath to said controller within a finite period of time while approximately 32 pins would be required to transfer said data from said datapath to said second bus within an equivalent, finite period of time. 
     
     
       13. The bridge of claim 11 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       14. The bridge of claim 11, wherein the first bus operating at a first bus speed includes a host bus operating at a host bus speed and wherein the second bus operating at a second bus speed includes a Peripheral Component Interconnect (PCI) bus operating at a PCI bus speed. 
     
     
       15. A computer system comprising: a processor coupled to a first bus, said first bus to operate at a first bus speed;   a peripheral device coupled to a second bus, said second bus to operate at a second bus speed; and   a bridge to couple said first bus to said second bus, enabling communication between said processor and said peripheral device, said bridge comprising a datapath to transfer data from said first bus to a controller at a datapath speed, said controller to transfer an address from said first bus to said second bus, said controller also to transfer said data from said datapath to said second bus.   
     
     
       16. The computer system of claim 15 wherein said datapath speed is approximately twice said second bus speed, and the number of pins that transfer said data from said datapath to said controller within a given period of time is approximately half the number of pins which would be required to transfer said data from said datapath to said second bus within said period of time. 
     
     
       17. The computer system of claim 15 wherein said datapath speed is approximately n times faster than said second bus speed, and the number of pins that transfer said data from said datapath to said controller within a given period of time is approximately 1/n times the number of pins which would be required to transfer said data from said datapath to said second bus within said period of time. 
     
     
       18. The computer system of claim 16 wherein approximately 16 pins transfer said data to said controller from said datapath. 
     
     
       19. The computer system of claim 15 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       20. The computer system of claim 16 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       21. The computer system of claim 15 wherein an additional load to said second bus is not required as a result of routing said data from said datapath through said controller rather than directly to said second bus. 
     
     
       22. The computer system of claim 15, wherein the first bus operating at a first bus speed includes a host bus operating at a host bus speed and wherein the second bus operating at a second bus speed includes a Peripheral Component Interconnect (PCI) bus operating at a PCI bus speed. 
     
     
       23. A computer system comprising: a processor coupled to a first bus, said first bus operating at a first bus speed;   a peripheral device coupled to a second bus, said second bus operating at a second bus speed; and   a bridge for coupling said first bus to said second bus for communicating information from said processor to said peripheral device, said bridge comprising a datapath, said datapath transferring data from said first bus to said controller at a datapath speed, said datapath speed being approximately n times faster than said second bus speed, and the number of pins that transfer said data to said controller within a given period of time is approximately 1/n times the number of pins which would be required to transfer said data to said second bus within said period of time, said controller transferring an address from said first bus to said second bus, said controller further transferring said data from said datapath to said second bus such that an additional load to said second bus is not required as a result of routing said data from said datapath through said controller rather than directly to said second bus.   
     
     
       24. The computer system of claim 23 wherein said datapath speed is approximately twice said second bus speed, and approximately 16 pins transfer said data from said datapath to said controller within said period of time while approximately 32 pins would be required to transfer said data from said datapath to said second bus within said period of time. 
     
     
       25. The computer system of claim 24 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       26. The computer system of claim 23, wherein the first bus operating at a first bus speed includes a host bus operating at a host bus speed and wherein the second bus operating at a second bus speed includes a Peripheral Component Interconnect (PCI) bus operating at a PCI bus speed. 
     
     
       27. An interface means for coupling a first bus means operating at a first bus speed to a second bus operating at a second bus speed comprising: a controller means for transferring an address from said first bus means;   a datapath means for transferring data from said first bus means; and   a means for transferring said address and said data to said second bus over a plurality of signal lines, each of said plurality of signal lines transferring at least a portion of said address and at least a portion of said data to said second bus, said plurality of signal lines contributing a first amount of load on said second bus that is less than a second amount of load that would be contributed on said second bus if each signal line of said plurality of signal lines were dedicated to transferring only said portion of said address.   
     
     
       28. The interface means of claim 27 further comprising a means for transferring said data from said datapath means to said controller means at a datapath speed, said controller means transferring said address and said data over said plurality of signal lines to said second bus. 
     
     
       29. The interface means of claim 27 further comprising a means for transferring said address from said controller means to said datapath means at a controller speed, said datapath means transferring said address and said data over said plurality of signal lines to said second bus. 
     
     
       30. The interface means of claim 27 further comprising a merger means, said merger means being coupled to said controller means, said controller means transferring said address to said merger means, said merger means also being coupled to said datapath means, said datapath means transferring said data to said merger means, said merger means transferring said address and said data over said plurality of signal lines to said second bus. 
     
     
       31. The interface means of claim 28 wherein said datapath speed is faster than said second bus speed and the number of pins that transfer said data from said datapath means to said controller means within a finite period of time is less than the number of pins which would be required to transfer said data from said datapath means directly to said second bus within an an equivalent, finite period of time. 
     
     
       32. The interface means of claim 29 wherein said controller speed is faster than said second bus speed, and the number of pins to transfer said address to said datapath within a finite period of time is less than the number of pins which would be required to transfer said address from said controller means to said second bus within an equivalent, finite period of time. 
     
     
       33. The interface means of claim 31 wherein approximately 16 pins transfer said data to said controller means from said datapath means. 
     
     
       34. The interface means of claim 28 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       35. The interface means of claim 32 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       36. The interface means of claim 27, wherein the first bus means operating at a first bus speed includes a host bus means operating at a host bus speed and wherein the second bus operating at a second bus speed includes a Peripheral Component Interconnect (PCI) bus operating at a PCI bus speed. 
     
     
       37. A computer system comprising: a processing means coupled to a first bus means, said first bus means to operate at a first bus speed;   a peripheral device means coupled to a second bus, said second bus to operate at a second bus speed; and   a bridge means for coupling said first bus means to said second bus for communicating information from said processing means to said peripheral device means, said bridge means comprising a datapath means, said datapath means to transfer data from said first bus means to a controller means at a datapath speed, said controller means to transfer an address from said first bus means to said second bus, said controller means also to transfer said data from said datapath means to said second bus.   
     
     
       38. The computer system of claim 37 wherein said datapath speed is approximately twice said second bus speed, and the number of signal lines that transfer said data from said datapath means to said controller means within a given period of time is approximately half the number of pins which would be required to transfer said data from said datapath means directly to said second bus within said period of time. 
     
     
       39. The computer system of claim 37 wherein said datapath speed is approximately n times faster than said second bus speed, and the number of signal lines that transfer said data from said datapath means to said controller means within a given period of time is approximately 1/n times the number of pins which would be required to transfer said data from said datapath means directly to said second bus within said period of time. 
     
     
       40. The computer system of claim 38 wherein approximately 16 pins transfer said data to said controller means from said datapath means. 
     
     
       41. The computer system of claim 37 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       42. The computer system of claim 38 wherein said first bus speed is equivalent to said datapath speed. 
     
     
       43. The computer system of claim 37 wherein an additional load to said second bus is not required as a result of routing said data from said datapath means through said controller means rather than directly to said second bus. 
     
     
       44. The computer system of claim 37, wherein the first bus means operating at a first bus speed includes a host bus operating at a host bus speed and wherein the second bus operating at a second bus speed includes a Peripheral Component Interconnect (PCI) bus operating at a PCI bus speed. 
     
     
       45. A method for transferring an address and data from a first bus that uses separate signal lines for said address and said data to a second bus that uses common, multiplexed signal lines for said address and said data, said method comprising the steps of: transferring at least a portion of said address from said first bus to said second bus through a plurality of pins coupled to said second bus; and   transferring at least a portion of said data from said first bus to said second bus through said plurality of pins wherein each pin of said plurality of pins transfers at least a portion of both said address and said data to said second bus.   
     
     
       46. The method of claim 45 wherein said step of transferring at least a portion of said address from said first bus to said second bus is done through a controller coupled to said plurality of pins, and said step of transferring at least a portion of said data from said first bus to said second bus includes the step of transferring through a datapath said portion of said data from said first bus to said controller. 
     
     
       47. The method of claim 45 wherein said step of transferring at least a portion of said data from said first bus to said second bus is done through a datapath coupled to said plurality of pins, and said step of transferring at least a portion of said address from said first bus to said second bus includes the step of transferring through a controller said portion of said address from said first bus to said datapath. 
     
     
       48. The method of claim 45 wherein said step of transferring at least a portion of said address from said first bus to said second bus includes the step of transferring through a controller said portion of said address from said first bus to a merger, said step of transferring at least a portion of said data from said first bus to said second bus includes the step of transferring through a datapath said portion of said data from said first bus to said merger, said merger is coupled to said plurality of pins, said first bus is a host bus, and said second bus is a Peripheral Component Interconnect (PCI) bus. 
     
     
       49. The method of claim 45 wherein said first bus is a host bus and said second bus is a Peripheral Component Interconnect (PCI) bus. 
     
     
       50. The method of claim 46 wherein said first bus is a host bus and said second bus is a Peripheral Component Interconnect (PCI) bus. 
     
     
       51. The method of claim 47 wherein said first bus is a host bus and said second bus is a Peripheral Component Interconnect (PCI) bus. 
     
     
       52. The method of claim 50 wherein said PCI bus operates at a PCI bus speed, said step of transferring through said datapath said portion of said data from said first bus to said controller is done at a datapath speed, said datapath speed being faster than said PCI bus speed, and the number of pins to transfer said data to said controller within a finite period of time is less than the number of pins which would be required to transfer said data from said datapath to said second bus within an equivalent, finite period of time. 
     
     
       53. The method of claim 51 wherein said PCI bus operates at a PCI bus speed, said step of transferring through said controller said portion of said address from said first bus to said datapath is done at a controller speed, said controller speed being faster than said PCI bus speed, and the number of pins to transfer said address to said datapath within a finite period of time is less than the number of pins which would be required to transfer said address from said controller to said second bus within an equivalent, finite period of time.