Method of manufacturing vertical MOSFET

Abstract

A semiconductor device includes a substrate (11), a first region (21) in the substrate (11) wherein the first region (21) has a first conductivity type, a second region (22) in the substrate (11) wherein the second region (22) is adjacent to the first region (21) and wherein the second region (22) has a second conductivity type different from the first conductivity type, and a third region (24) in the substrate (11) wherein the third region (24) overlaps the first and second regions (21, 22) and wherein the third region (24) has a damaged crystalline structure.

We claim: 
     
       1. A method of manufacturing a semiconductor device comprising: providing a semiconductor substrate;   forming a first doped region in the semiconductor substrate, the first doped region having a first conductivity type;   annealing the first doped region:   forming a second doped region in the first doped region after annealing the first doped region, the second doped region having a second conductivity type different from the first conductivity type;   annealing the first and second doped regions; and   damaging a portion of the first doped region to reduce a lifetime of minority carriers in the first doped region, the portion of the first doped region adjacent to the second doped region.   
     
     
       2. The method of claim 1 wherein the steps of forming the first doped region and forming the second doped region comprise forming a vertical metal-oxide-semiconductor field effect transistor wherein the second doped region is a source region for the vertical metal-oxide-semiconductor field effect transistor and wherein the vertical metal-oxide-semiconductor field effect transistor has a parasitic bipolar transistor wherein the portion of the first doped region is a base region for the parasitic bipolar transistor. 
     
     
       3. The method of claim 1 wherein the step of forming the second doped region includes forming a p-n junction between the first and second doped regions and wherein the step of damaging the portion of the first doped region includes damaging a portion of the p-n junction. 
     
     
       4. The method of claim 1 wherein the step of damaging the portion of the first doped region includes implanting ions into the portion of the first doped region. 
     
     
       5. The method of claim 4 further comprising: forming a gate electrode over a portion of the semiconductor substrate wherein the gate electrode has a gate opening wherein the step of forming the first doped region includes implanting the first doped region and wherein the step of forming the second doped region includes implanting the second doped region and wherein the steps of implanting the first doped region and implanting the second doped region include self-aligning the first and second doped regions to the gate opening;   depositing a dielectric layer over the gate electrode, a portion of the dielectric layer in the gate opening; and   etching a dielectric opening in the portion of dielectric layer wherein the step of implanting the ions includes self-aligning the ions to the dielectric opening.   
     
     
       6. The method of claim 4 further comprising forming a gate electrode over a portion of the semiconductor substrate wherein the steps of forming the first doped region, forming the second doped region, and implanting the ions include self-aligning the first doped region, the second doped region, and the ions to the gate electrode. 
     
     
       7. The method of claim 4 further comprising: forming a gate electrode over a portion of the semiconductor substrate; and   forming a dielectric layer over the gate electrode wherein the step of implanting the ions includes self-aligning the ions to the dielectric layer.   
     
     
       8. The method of claim 1 further comprising annealing the second doped region only after the step of damaging the portion of the first doped region. 
     
     
       9. The method of claim 1 wherein the step of damaging the portion of the first doped region includes damaging the portion of the first doped region before the step of forming the second doped region. 
     
     
       10. The method of claim 1 wherein the step of providing the semiconductor substrate includes providing the semiconductor substrate with a crystalline structure and wherein the step of damaging the portion of the first doped region includes damaging the crystalline structure of the portion of the first doped region. 
     
     
       11. A method of fabricating a semiconductor component comprising: providing a substrate having a first surface and a second surface opposite the first surface;   forming a gate electrode over a portion of the first surface of the substrate;   self-aligning a doped region to the gate electrode, the doped region formed in the substrate wherein a first portion of the doped region is a channel region;   self-aligning a source region to the gate electrode, the source region formed in the substrate, the source region adjacent to the first portion of the doped region, and a second portion of the doped region underlying the source region; and   implanting ions with a first implant energy into the source region and into the second portion of the doped region, the ions comprised of titanium and a peak concentration of the ions implanted into the second portion of the doped region.   
     
     
       12. The method of claim 11 wherein the step of implanting the ions includes providing the ions in a portion of the channel region. 
     
     
       13. The method of claim 11 further comprising implanting the ions with a second implant energy to modify a concentration profile of the ions in the substrate. 
     
     
       14. The method of claim 11 wherein the step of self-aligning the source region includes forming an emitter region for a parasitic bipolar transistor and wherein the step of implanting the ions includes forming recombination centers in the second portion of the doped region to reduce an emitter efficiency of the parasitic bipolar transistor. 
     
     
       15. The method of claim 11 further comprising: etching an opening in the gate electrode wherein the steps of self-aligning the doped region, self-aligning the source region, and implanting the ions includes self-aligning the doped region, the source region, and the ions to a portion of the opening;   forming a source electrode in the opening wherein the source electrode is electrically coupled to the source region; and   forming a drain electrode adjacent to the second surface of the substrate.   
     
     
       16. A method of making an electronic device comprising: providing a semiconductor substrate;   forming an implant mask over the semiconductor substrate, the implant mask having a hole;   forming a first region in the semiconductor substrate, the first region having a first conductivity type and self-aligned to the hole in the implant mask;   forming a second region in the semiconductor substrate and in the first region, the second region having a second conductivity type and self-aligned to the hole in the implant mask; and   damaging a portion of the first region to reduce the minority carrier lifetime in the first region, the portion of the first region self-aligned to the hole in the implant mask.   
     
     
       17. The method of claim 16 wherein damaging the portion of the first region further comprises forming the portion of the first region contiguous with the second region. 
     
     
       18. The method of claim 16 wherein forming the first region comprises providing a doping concentration for the first region, wherein forming the second region comprises providing a doping concentration for the second region, and wherein damaging the portion of the first region comprises keeping the doping concentration of the first region and the doping concentration of the second region substantially unaltered. 
     
     
       19. The method of claim 16 wherein forming the second region includes keeping the second region within the first region. 
     
     
       20. The method of claim 16 wherein forming the second region includes keeping the second region within the portion of the first region.