Integrated circuit structure with interconnect formed along walls of silicon island

Abstract

Insulating trenches (2) in the silicon layer of an SOI substrate that extend onto the insulating layer of the SOI substrate define silicon islands (3). At least one of the silicon islands (3) is an interconnect segment (3a) by a diffusion zone that is arranged at the walls of the surrounding trench (2) and that is formed by drive-out from an occupation layer introduced into the trench. The interconnect segment (3a) is suitable as an underpass for crossing interconnects (6a,6b) or as an additional metallization level.

What is claimed is: 
     
       1. An integrated circuit structure, comprising: an SOI substrate that encompasses a silicon wafer, an insulating layer arranged on the SOI substrate and a monocrystalline silicon layer arranged on the insulating layer;   insulating trenches that respectively extend from a surface of the monocrystalline silicon layer down onto the insulating layer and that define silicon islands in the monocrystalline silicon layer, said silicon islands being respectively completely surrounded by respective insulating trenches and being thereby insulated from one another; and   at least one interconnect segment formed in one of the silicon islands by a diffusion zone arranged along surrounding trench walls of the insulating trench associated with said one of the silicon islands.   
     
     
       2. The integrated circuit arrangement according to claim 1, wherein an intermediate oxide layer is arranged on a surface of the monocrystalline silicon layer; wherein the intermediate oxide layer has a first via hole and a second via hole, each of the first and second via holes respectively meeting the interconnect segment and the first and second via holes being provided with a first contact and with a second contact, respectively; and   wherein a first conductive structure that is connected to the first contact and a second conductive structure that is connected to the second contact are arranged on a surface of the intermediate oxide layer.   
     
     
       3. The integrated circuit structure according to claim 2, wherein each of the first conductive structure and the second conductive structure have respective contacts to components that are arranged in two different silicon islands. 
     
     
       4. The integrated circuit structure according to claim 2, wherein the first conductive structure and the second conductive structure are respectively parts of an interconnect arranged on the surface of the intermediate oxide layer and interrupted in the region of the interconnect segment at the surface of the intermediate oxide layer. 
     
     
       5. The integrated circuit structure according to claim 1, wherein the dopant concentration of the diffusion zone in the interconnect segment is in the range from 10 18  to 10 21  cm -3 . 
     
     
       6. The integrated circuit structure according to claim 1, wherein further insulating trenches, that respectively extend from the surface of the monocrystalline silicon layer down onto the insulating layer and that divide the silicon island into silicon strips connected to one another, are arranged in the silicon island that is an interconnect segment, and wherein further diffusion zones are provided along the walls of the further insulating trenches in the silicon island that is an interconnect segment.   
     
     
       7. An integrated circuit structure, comprising: an SOI substrate that encompasses a silicon wafer, an insulating layer arranged on the SOI substrate and a monocrystalline silicon layer arranged on the insulating layer;   insulating trenches that respectively extend from a surface of the monocrystalline silicon layer down onto the insulating layer and that define at least one silicon island in the monocrystalline silicon layer, said at least one silicon island being respectively completely surrounded by respective insulating trenches;   further insulating trenches, that respectively extend from the surface of the monocrystalline silicon layer down onto the insulating layer and that divide the at least one silicon island into silicon strips connected to one another, are arranged in the at least one silicon island;   further diffusion zones are provided along the walls of the further insulating trenches in the at least one silicon island; and   at least one interconnect segment formed in the at least one silicon island by a diffusion zone arranged along surrounding trench walls of the insulating trench associated with the at least one silicon islands.   
     
     
       8. The integrated circuit arrangement according to claim 7, wherein an intermediate oxide layer is arranged on a surface of the monocrystalline silicon layer; wherein the intermediate oxide layer has a first via hole and a second via hole, each of the first and second via holes respectively meeting the interconnect segment and the first and second via holes being provided with a first contact and with a second contact, respectively; and   wherein a first conductive structure that is connected to the first contact and a second conductive structure that is connected to the second contact are arranged on a surface of the intermediate oxide layer.   
     
     
       9. The integrated circuit structure according to claim 7, wherein each of the first conductive structure and the second conductive structure have respective contacts to components that are arranged in two different silicon islands. 
     
     
       10. The integrated circuit structure according to claim 7, wherein the first conductive structure and the second conductive structure are respectively parts of an interconnect arranged on the surface of the intermediate oxide layer and interrupted in the region of the interconnect segment at the surface of the intermediate oxide layer. 
     
     
       11. The integrated circuit structure according to claim 7, wherein the dopant concentration of the diffusion zone in the interconnect segment is in the range from 10 18  to 10 21  cm -3 .