Method and system for performance monitoring of misaligned memory accesses in a processing system

Abstract

A method and system for monitoring performance of a processing system, the processing system including a plurality of performance monitor counters (PMCs) and at least one monitor mode control register (MMCR) to configure the operations of at least one of the PMCs, includes identifying misaligned data items, and determining a performance penalty of misaligned data accesses during a predetermined sampling period.

What is claimed is: 
     
       1. A method for monitoring performance of a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, the method comprising: (a) identifying misaligned data items: and   (b) determining a performance penalty due to misaligned data accesses during a predetermined sampling period, wherein step (b) further comprises: (b1) determining a first difference value between the number of cycles required for misaligned loads and for aligned loads;   (b2) determining a second difference between a number of cycles required for misaligned stores and for aligned stores;   (b3) identifying the performance penalty as a combination of the first difference value for the counted number of misaligned loads and the second difference value for the counted number of misaligned stores.     
     
     
       2. The method of claim 1 further comprising: (c) altering at least one component of code to reduce the number of misaligned accesses to improve system performance.   
     
     
       3. The method of claim 1 further comprising: (c) altering at least one hardware component of the processing system to reduce the time required to access misaligned data to improve system performance.   
     
     
       4. The method of claim 1 wherein step (b) further comprises: counting a number of misaligned load operations during the predetermined sampling period.   
     
     
       5. The method of claim 4 wherein the step of counting further comprises: counting a number of misaligned load operations that are cache hits for first and second accesses during the predetermined sampling period.   
     
     
       6. The method of claim 1 wherein step (b2) further comprises: counting a number of misaligned store operations during the predetermined sampling period.   
     
     
       7. The method of claim 6 wherein the step of counting further comprises: counting a number of misaligned store operations that are cache hits for first and second accesses during the predetermined sampling period.   
     
     
       8. A system for monitoring performance of a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, the system comprising a circuit for identifying misaligned data items: and for determining a performance penalty of misaligned data accesses during a predetermined sampling period, in which the circuit further provides for determining a first difference value between the number of cycles required for misaligned loads and for aligned loads; for determining a second difference between a number of cycles required for misaligned stores and for aligned stores; and for identifying the performance penalty as a combination of the first difference value for the counted number of misaligned loads and the second difference value for the counted number of misaligned stores. 
     
     
       9. The system of claim 8 in which the circuit further provides for altering at least one component of code to reduce the number of misaligned accesses to improve system performance. 
     
     
       10. The system of claim 8 in which the circuit further provides for altering at least one hardware component of the processing system to reduce the time spent required to access misaligned data to improve system performance. 
     
     
       11. The system of claim 8 in which the circuit further provides for counting a number of misaligned load operations during the predetermined sampling period. 
     
     
       12. The system of claim 11 in which the circuit further provides for counting a number of misaligned load operations that are cache hits for first and second accesses during the predetermined sampling period. 
     
     
       13. The system of claim 8 in which the circuit further provides for counting a number of misaligned store operations during the predetermined sampling period. 
     
     
       14. The system of claim 13 in which the circuit further provides for counting a number of misaligned store operations that are cache hits for first and second accesses during the predetermined sampling period. 
     
     
       15. A computer readable medium containing program instructions for monitoring performance of a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, the instructions comprising: (a) identifying misaligned data items stored in memory of the processing system; and   (b) determining a performance penalty due to misaligned data accesses in the processing system during a predetermined sampling period wherein step (b) further comprises: (b1) determining a first difference value between the number of cycles required for misaligned loads and for aligned loads:   (b2) determining a second difference between a number of cycles required for misaligned stores and for aligned stores:   (b3) identifying the performance penalty as a combination of the first difference value for the counted number of misaligned loads and the second difference value for the counted number of misaligned stores.