Ferroelectric memory and recording device using the same

Abstract

A ferroelectric memory having a thin ferroelectric film sandwiched between a pair of electrodes as a memory cell includes a first pulse generating circuit for applying a first pulse having a voltage Ve higher than a coercive voltage Vc of the thin ferroelectric film to the memory cell, thereby forming a polarized state in a first direction of two states of polarization, a second pulse generating circuit for applying to the memory cell a second pulse having a voltage Vw whose polarity is opposite to a polarity of the first pulse applied by the first pulse generating circuit, thereby forming a partially polarized state containing both domains having polarization in the first direction and domains having polarization in a second direction opposite to the first direction, and an analog recording unit for performing analog recording by controlling the partially polarized state by using the second pulse generated by the second pulse generating circuit.

What is claimed is: 
     
       1. A ferroelectric memory having a thin ferroelectric film sandwiched between a pair of electrodes as a memory cell, comprising: first pulse applying means for applying a first pulse having a voltage Ve higher than a coercive voltage Vc of said thin ferroelectric film to said memory cell, thereby forming a polarized state in a first direction of two states of polarization;   second pulse applying means for applying to said memory cell a second pulse having a voltage Vw whose polarity is opposite to a polarity of the first pulse applied by said first pulse applying means, thereby forming a partially polarized state containing both domains having polarization in the first direction and domains having polarization in a second direction opposite to the first direction; and   analog recording means for performing analog recording by controlling the partially polarized state by using the second pulse applied by said second pulse applying means.   
     
     
       2. A memory according to claim 1, further comprising a switching element added to each memory cell. 
     
     
       3. A memory according to claim 2, wherein said switching element is a three-terminal selective switching element added to each memory cell, one of said pair of electrodes is connected to a current control terminal of said three-terminal selective switching element, and a cell selection control signal is supplied to said current control terminal. 
     
     
       4. A memory according to claim 3, wherein said three-terminal selective switching element is a field-effect transistor (FET), one of said pair of electrodes is connected to a source or a drain of the FET, and a cell selection control signal is supplied to a gate of the FET. 
     
     
       5. A memory according to any one of claims 1 and 2, wherein an absolute value of a magnitude Ve of the first pulse and an absolute value of a magnitude Vw of the second pulse satisfy Vw≦We. 
     
     
       6. A memory according to claim 1, wherein a pulse width Ww of the second pulse is 1% to 300% of a pulse width We of the first pulse. 
     
     
       7. A memory according to claim 4, wherein a pulse width We of the first pulse and a pulse width Ww of the second pulse satisfy Ww≦We. 
     
     
       8. A memory according to claim 1, wherein a polarization amount of the partially polarized state is 10% to 90% of a polarization amount of the first polarized state. 
     
     
       9. A device according to claim 1, wherein an equalizing circuit is arranged between an output of a memory cell and an output terminal of a memory and forms an analog operation lookup table in accordance with an input-output relationship of an analog signal previously written in said memory cell, and an equalized output is obtained by inputting an output signal from the memory cell to the lookup table. 
     
     
       10. A device according to claim 1, wherein an equalizing circuit is arranged between an output of a memory cell and an output terminal of a memory and forms a digital operation lookup table in accordance with an input-output relationship of an analog signal previously written in said memory cell, and an equalized output is obtained by A/D-converting an output signal from the memory cell, inputting this converted signal to the lookup table, and D/A-converting an output from the lookup table. 
     
     
       11. A device according to claim 1, wherein an equalizing table is formed each time a certain amount of information is written, and an equalized output is obtained by using the equalizing table when the information is read. 
     
     
       12. A device according to claim 11, wherein preprocessing for forming an equalizing table is performed before a memory recording operation, and an equalized output is obtained by using the equalizing table when a read operation is performed. 
     
     
       13. A device according to claim 12, wherein an equalizing table is formed before a memory read operation, and an equalized output is obtained by using the equalizing table when a read operation is performed. 
     
     
       14. A device according to any one of claims 11, 12, and 13, wherein the equalizing table is formed by using an equalizing cell arranged in the same chip and having the same configuration as the memory cell. 
     
     
       15. A device according to any one of claims 11, 12, and 13, wherein an equalizing cell has the same configuration as said memory cell. 
     
     
       16. A device according to any one of claims 11, 12, and 13, wherein the equalizing table is formed by using inverse transform of an operation matrix indicating an input-output relationship of an equalizing cell. 
     
     
       17. A device according to any one of claims 11, 12, and 13, wherein an output voltage is represented by a polynomial of an input voltage in order to indicate an input-output relationship of an equalizing cell, and the equalizing table is formed by using inverse transform of the polynomial. 
     
     
       18. A device according to claim 1, wherein analog recording is performed by using a linear region in a voltage-charge characteristic of said thin ferroelectric film. 
     
     
       19. A device according to claim 1, wherein analog recording is performed by using a region in which a shift from a linear region is not more than 50% in a voltage-charge characteristic of said thin ferroelectric film. 
     
     
       20. A device according to any one of claims 18 and 19, wherein an amplitude center of an analog signal is set in a center of a linear region in a voltage-charge characteristic of said thin ferroelectric film.