Method providing, an enriched source side extension and a lightly doped extension

Abstract

A semiconductor device having a lightly doped drain ("LDD") at a first dopant concentration and a source side extension ("SSE") at a second, higher, dopant concentration is provided. This allows for increased current saturation | DSAT due to a lower resistance at or near the source and thus increases semiconductor switching speed without hot carrier creation due to lighter doped, more graded body-drain junction. A method for manufacturing the semiconductor device, in particular a metal oxide semiconductor ("MOS") transistor, is also provided. A first photoresist mask is positioned over a portion of a polysilicon gate and a subsequently formed drain region of a transistor substrate. The transistor may be an N-channel or P-channel transistor. The SSE is formed using a higher dopant concentration than used in the LDD. A second photoresist mask is then used to cover the SSE region and portion of the polysilicon gate while a relatively lower implant dopant dose is used to form the LDD. Oxide spacers and heavy implant concentrations are then used to form a source and a drain.

What is claimed is: 
     
       1. A method for manufacturing a semiconductor device, comprising the steps of: (a) forming a region in a substrate having a first conductive type;   (b) forming a gate on the first conductive type region;   (c) forming a first mask over a first portion of the first conductive type region;   (d) implanting a dopant having a lightly doped charge of a second conductive type into a second portion of the first conductive type region;   (e) forming a second mask on the second portion; and,   (f) implanting a dopant having a lightly doped charge of a second conductive type into the first portion.   
     
     
       2. The method of claim 1, wherein the method further includes the steps of: (a) forming a first and a second spacer adjacent the gate; and,   (b) implanting a dopant having a heavily doped charge of a second conductive type into the first and second portions.   
     
     
       3. The method of claim 1, wherein the first conductive type is a P-type and the second conductive type is a N-type. 
     
     
       4. The method of claim 1, wherein the first conductive type is a N-type and the second conductive type is a P-type. 
     
     
       5. The method of claim 1, wherein a lightly doped charge concentration used in forming the first portion is greater than a lightly doped charge concentration used in forming the second portion. 
     
     
       6. The method of claim 2, wherein a lightly doped charge concentration is an order of magnitude less than a heavily doped charge concentration used in forming the first and second portion. 
     
     
       7. A method for manufacturing a complimentary metal oxide semiconductor("CMOS") device having a positively charged P-well region and a negatively charged N-well region, comprising the steps of: (a) forming a first gate on the P-well region;   (b) forming a second gate on the N-well region;   (c) forming a first mask on the N-well region and a first portion of the P-well region;   (d) implanting a dopant having a light donor dose into a second portion of the P-well region;   (e) forming a second mask on the N-well region and the second portion of the P-well region;   (f) implanting a dopant having a light donor dose into the first portion of the P-well region;   (g) forming a third mask on the P-well region and a first portion of the N-well region;   (h) implanting a dopant having a light acceptor dose into a second portion of the N-well region;   (i) forming a fourth mask on the P-well region and the second portion of the N-well region;   (j) implanting a dopant having a light acceptor dose into the first portion of the N-well region;   (k) forming respective oxide spacers adjacent to the first and second gates;   (l) forming a fifth mask on the N-well region;   (m) implanting a dopant having a heavy donor dose into to the P-well region;   (n) forming a mask on the P-well region; and,   (o) implanting a heavy doped acceptor dose into to the N-well region.   
     
     
       8. The method of claim 7, wherein the light acceptor dose implanted into the first region of the P-well region is different than the light acceptor dose implanted into the second region of the P-well region. 
     
     
       9. The method of claim 7, wherein the lightly doped charge in the first and second portion the N-well region are used to form a lightly doped drain ("LDD") and source side extension ("SSE"). 
     
     
       10. The method of claim 7, wherein the gates are polysilicon gates. 
     
     
       11. The method of claim 7, wherein the masks are photoresist masks. 
     
     
       12. The method of claim 7, wherein the implanting of the heavy donor dose includes the step of forming a first source and first drain in the CMOS device. 
     
     
       13. The method of claim 12, wherein the implanting of the heavy acceptor dose includes the step of forming a second source and a second drain in the CMOS device. 
     
     
       14. The method of claim 7, wherein the light implant dose used in step (d) is about an order of magnitude less than the heavily doped implant concentration used in step (m).