In-circuit emulator in which abrupt and deferred arming and disarming of several events on a microprocessor chip are controlled using a single-input pin

Abstract

An in-circuit emulator on an integrated circuit chip having an input pin for externally triggering on-chip break mechanisms. A first break logic having a first arm input is connected to an instruction pointer counter (IP counter). The first break logic matches the IP counter to a first instruction execution address. A second break logic having a second arm input is connected to the IP counter. The second break logic matches the IP counter to a second instruction execution address and a third instruction execution address occurring a fixed time interval after the second instruction execution address in a mutistage pipe line of instructions. A sequencer logic connected to the input pin, the first arm input and the second arm input activates the second arm input after the input pin has been active for 1 cycle. The sequencer logic activates the first arm input after the input pin has been active for 2 cycles. Also provided is a fast and permanent break logic having an abrupt permanent beak input connected to the sequencer and a fast break input connected to the sequencer. The sequencer activates the abrupt permanent beak input after the input pin has been active for 3 cycles. The sequencer activates the fast break input after the input pin has been active for 4 cycles. This allows external abrupt and deferred arming and disarming of internal fast and permanent events, using the same input pin as was used in the past for just an abrupt break.

What is claimed is: 
     
       1. An in-circuit emulator comprising: an input pin;   a sequencer coupled to the input pin, the sequencer having a first output being active upon a condition that the input pin is active for one cycle, and a second output being active upon a condition that the input pin is active for two cycles;   a first break logic coupled to the first output, the first break logic having an output; and   a second break logic coupled to the second output, the second break logic having an output.   
     
     
       2. The emulator in accordance with claim 1 wherein the sequencer has an abrupt fast break output and an abrupt permanent break output, the emulator further comprising: a third break logic having a first output being active upon a condition that the input pin is active for three cycles, and a second output being active upon a condition that the input pin is active for four cycles; and   a fourth break logic having an output coupled to the sequencer.   
     
     
       3. The emulator in accordance with claim 2 wherein the emulator further comprises: a status register being connected to the output of the fourth break logic, to the output of the first break logic and to the output of the second break logic, the status register recording a cause of a break in response to one of the output of the fourth break logic, the output of the first break logic and the output of the second break logic.   
     
     
       4. The emulator in accordance with claim 2 wherein the emulator further comprises: an instruction pointer (IP) counter;   a control register coupled to a plurality of input pins, the control register having a first output and a second output; and   an IP matcher having a first output and a second output, the IP matcher coupled to the IP counter and the first and second outputs of the control register, the IP matcher asserting the first output of the IP matcher upon a condition that the first output of the control register and the IP counter are equal, and the IP matcher asserting the second output of the IP matcher upon the condition that the second output of the control register and the IP counter are equal.   
     
     
       5. The emulator in accordance with claim 1 wherein the emulator further comprises: a status register being connected to the output of the first break logic and to the output of the second break logic, and the status register recording a cause of a break in response to one of the output of the first break logic and the output of the second break logic.   
     
     
       6. The emulator in accordance with claim 1 wherein the emulator further comprises: an instruction pointer (IP) counter;   a control register coupled to a plurality of input pins, the control register having a first output and a second output;   an IP matcher having a first output and a second output, the IP matcher coupled to the IP counter and the first and second output of the control register, the IP matcher asserting the first output of the IP matcher upon a condition that the first output of the control register and the IP counter are equal and the IP matcher asserting the second output of the IP matcher upon a condition that the second output of the control register and the IP counter are equal;   the first break logic coupled to the second output of the IP matcher, the first break logic asserting the output of the first break logic in response to the second output of the IP matcher; and   the second break logic coupled to the first output of the IP matcher, the second break logic asserting the output of the second break logic in response to the first output of the IP matcher.   
     
     
       7. An in-circuit emulator comprising: an input pin;   a sequencer coupled to the input pin, the sequencer having a first output being active upon a condition that a second output is asserted and that the input pin is active for four cycles, a third output being active upon a condition that the second output is asserted and the input pin is active for two cycles, a fourth output being active upon a condition that the second output is asserted and that the input pin is active for two cycles, a fifth output being active upon a condition that the second output is asserted and that the input pin is active for one cycle, and a sixth output;   a first break logic coupled to the fourth output having an output;   a second break logic coupled to the fifth output having an output;   a third break logic having a first output and a second output;   a fourth break logic coupled to the second output, the first output and the third output, the fourth break logic having an output;   a first logic coupled to the sixth output, the first and second outputs of the third break logic, the first logic having the second output that is asserted in response to the sixth output; and   a status register coupled to the output of the first break logic, the output of the second break logic and the output of the fourth break logic, the status register recording a cause of a break in response to one of the output of the first break logic, the output of the second break logic and the output of the fourth break logic.   
     
     
       8. The emulator in accordance with claim 7 wherein the emulator further comprises: an instruction pointer (IP) counter;   a control register coupled to a plurality of input pins, the control register having a first output and a second output;   an IP matcher having a first output and a second output, the IP matcher coupled to the IP counter and the first and the second outputs of the control register, the IP matcher asserting the first output of the IP matcher upon a condition that the first output of the control register and the IP counter are equal, and the IP matcher asserting the second output of the IP matcher upon a condition that the second output of the control register and the IP counter are equal;   the first break logic coupled to the second output of the control register, the first break logic asserting the fourth output in response to the second output of the control register; and   the second break logic coupled to the first output of the control register, the second break logic asserting the fifth output in response to the first output of the control register.   
     
     
       9. An in-circuit emulator comprising: an input pin;   a plurality of break logic circuits each having at least one output; and   a sequencer, coupled to the input pin and the plurality of break logic circuits, wherein the sequencer selects one of the plurality of break logic circuits in response to a trigger and the number of cycles the input pin is asserted.   
     
     
       10. The in-circuit emulator of claim 9, further comprising: a status register, coupled to the at least one output of the plurality of break logic circuits, operative to store the status of each of the at least one output of the plurality of break logic circuits when one of the plurality of break logic circuits is selected.   
     
     
       11. An in-circuit emulator comprising: an input pin;   a sequencer coupled to the input pin, the sequencer having a first output being active upon a first condition from the input pin and a second output being active upon a second condition from the input pin;   a first break logic coupled to the first output, the first break logic having an output; and   a second break logic coupled to the second output, the second break logic having an output.   
     
     
       12. An in-circuit emulator comprising: an input pin;   a sequencer coupled to the input pin, the sequencer having an arm Cluster A output being active upon a condition that the input pin is active for one cycle, and an arm Cluster B output being active upon a condition that the input pin is active for two cycles;   an instruction pointer (IP) counter;   a control register coupled to a plurality of input pins, the control register having an IP match 0 output and an IP match 1 output;   an IP matcher having an IP 0 match output and an IP 1 match output, the IP matcher coupled to the IP counter, the IP match 0 output and the IP match 1 output, the IP matcher asserting the IP 0 match output upon a condition that the IP match 0 output and the IP counter are equal, and the IP matcher asserting the IP 1 match output upon a condition that the IP match 1 output and the IP counter are equal;   a Cluster A break logic coupled to the IP 1 match output and the arm Cluster A output, the Cluster A break logic asserting a cause Cluster A output in response to the IP 1 match output; and   a Cluster B break logic coupled to the IP 0 match output and the arm Cluster B output, the Cluster B break logic asserting a cause Cluster B output in response to the IP 0 match output.   
     
     
       13. An in-circuit emulator comprising: an input pin;   a sequencer coupled to the input pin, the sequencer having an abrupt fast break output being active upon a condition that a mode go output is asserted and that the input pin is active for four cycles, an abrupt permanent break output being active upon a condition that the mode go output is asserted and the input pin is active for three cycles, an arm Cluster A output being active upon a condition that the mode go output is asserted and that the input pin is active for two cycles, and arm Cluster B output being active upon a condition that the mode go output is asserted and that the input pin is active for one cycle and a go output;   a Cluster A break logic coupled to the arm Cluster A output having a cause Cluster A output;   a Cluster B break logic coupled to the arm Cluster B output having a cause Cluster B output;   a fast and permanent break logic having a fast break output and a permanent break output;   an abrupt break logic coupled to the mode go output, the abrupt fast break output and the abrupt permanent break output, the abrupt break logic having a cause abrupt output;   a mode logic coupled to the go output, the fast break output and the permanent break output, the mode logic having the mode go output that is asserted in response to the go output; and   a status register coupled to the cause Cluster A output, the cause Cluster B output and the cause abrupt output, the status register recording a cause of a break in response to one of the cause abrupt output, the cause Cluster A output and the cause Cluster B output.