External write pulse control method and structure

Abstract

A method and control circuit structure for externally controlling the width of a write pulse of a synchronous integrated circuit memory device is disclosed. The method and control circuit provide for a test mode in which the width of the write pulse of the synchronous integrated circuit memory device may be externally controlled to be entered. After entering the test mode, the start of a write pulse of the synchronous integrated circuit memory device is triggered by a transition of a clock signal from a first logic state to a second logic state. The termination of the write pulse is accomplished by selective manipulation of an external control signal external to the synchronous integrated circuit memory device.

What is claimed is: 
     
       1. A method for externally controlling the width of a write pulse of a synchronous integrated circuit memory device, comprising the steps of: entering a test mode in which the width of the write pulse of the synchronous integrated circuit memory device may be externally controlled;   triggering the start of a write pulse of the synchronous integrated circuit memory device by a transition of a clock signal from a first logic state to a second logic state; and   selectively terminating the write pulse of the synchronous integrated circuit memory device by selective manipulation of an external control signal.   
     
     
       2. The method of claim 1, wherein the step of selectively terminating the write pulse of the synchronous integrated circuit memory device is accomplished by transition of the external control signal from a first logic level to a second logic level. 
     
     
       3. The method of claim 2, wherein the first logic state is equal to the first logic level and the second logic state is equal to the second logic level. 
     
     
       4. The method of claim 2, wherein transition of the external control signal from a first logic level to a second logic level causes the synchronous integrated circuit device to exit a writing state to go to a non-writing state. 
     
     
       5. The method of claim 1, wherein the external control signal is the clock signal or a derivative signal of the clock signal. 
     
     
       6. The method of claim 1, wherein during a normal operating mode, the synchronous integrated circuit memory device is internally self-timed. 
     
     
       7. A method for externally controlling the width of a write pulse of a synchronous integrated circuit memory device, comprising the steps of: entering a test mode in which the width of the write pulse of the synchronous integrated circuit memory device may be externally controlled;   triggering the start of a write pulse of the synchronous integrated circuit memory device by a transition of a clock signal from a first logic state to a second logic state;   selectively terminating the write pulse of the synchronous integrated circuit memory device by selective manipulation of an external control signal;   determining an optimal pulse width; and   blowing a fuse element to set the write pulse to the optimal pulse width.   
     
     
       8. A method for externally controlling the width of a write pulse of a synchronous integrated circuit memory device, comprising the steps of: entering a test mode in which the width of the write pulse of the synchronous integrated circuit memory device may be externally controlled;   triggering the start of a write pulse of the synchronous integrated circuit memory device by a transition of a clock signal from a first logic state to a second logic state; and   selectively terminating the write pulse of the synchronous integrated circuit memory device by selective manipulation of an external control signal, wherein upon changing the write pulse of the synchronous integrated circuit memory device by selectively terminating the write pulse comprising the additional step of: using the write pulse of the synchronous integrated circuit memory device as a screen to identify one or more marginal cells of the synchronous integrated circuit memory device.     
     
     
       9. The method of claim 8, wherein after the step of using the write pulse of the synchronous integrated circuit memory device as a screen to identify one or more marginal cells, comprising the additional step of: replacing the one or more marginal cells of the synchronous integrated circuit memory device with one or more redundant elements.   
     
     
       10. The method of claim 8, wherein after the step of using the write pulse of the synchronous integrated circuit memory device as a screen to identify one or more marginal cells, comprising the additional step of: discarding the one or more marginal cells of the synchronous integrated circuit memory device.   
     
     
       11. Control circuitry of a synchronous integrated circuit memory device that provides for externally controlling the width of a write pulse of the synchronous integrated circuit memory device, comprising: a first logic element that receives a write test signal as a first input signal and a first signal as a second input signal and that generates a first speed grade signal;   a second logic element that receives the write test signal as a first input signal and a second signal as a second input signal and that generates an output signal;   a multiplexer that receives a third signal as a first input signal and a clock signal as a second input signal and that generates an output signal when operational, wherein the multiplexer is controlled to be operational by the output signal generated by the second logic element; and   a third logic element that receives the output signal of the multiplexer as a first input signal and an external control signal as a second input signal and that generates a control output signal,   wherein during a test mode of the synchronous integrated circuit memory device, a transition of the clock signal from a first logic state to a second logic state triggers the start of a write cycle of the synchronous integrated circuit memory device and the write pulse of the synchronous integrated circuit memory device is selectively terminated by selective manipulation of the external control signal.   
     
     
       12. The control circuit of claim 11, wherein the write pulse of the synchronous integrated circuit memory device is selectively terminated by transition of the external control signal from a first logic level to a second logic level. 
     
     
       13. The control circuit of claim 12, wherein the first logic state is equal to the first logic level and the second logic state is equal to the second logic level. 
     
     
       14. The control circuit of claim 12, wherein transition of the external control signal from a first logic level to a second logic level causes the synchronous integrated circuit device to exit a writing state to go to a non-writing state. 
     
     
       15. The control circuit of claim 11, wherein the control circuitry further comprises: a fourth logic element that receives the write test signal as a first input signal and a fourth signal as a second input signal and that generates a second speed grade signal.   
     
     
       16. The control circuit of claim 15, wherein the control circuitry further comprises: a first programmable element having an output signal that is gated with an output signal of the first logic element to produce the first speed grade signal, wherein the first programmable element is capable of being programmed to speed up the first speed grade signal; and   a second programmable element having an output signal that is gated with an output signal of the fourth logic element to produce the second speed grade signal, wherein the second programmable element is capable of being programmed to speed up the second speed grade signal.   
     
     
       17. The control circuit of claim 16, wherein the first programmable element is a first fuse and the second programmable element is a second fuse, and the first programmable element is programmed by blowing the first fuse and the second programmable element is programmed by blowing the second fuse. 
     
     
       18. The control circuit of claim 17, wherein the first programmable element and the second programmable element are programmed by a power-on reset signal. 
     
     
       19. The control circuit of claim 15, wherein the control circuitry further comprises: a first programmable element having an output signal that is gated with an output signal of the second logic element to produce the second speed grade signal, wherein the first programmable element is capable of being programmed to speed up the second speed grade signal.   
     
     
       20. The control circuit of claim 19, wherein the first programmable element is a fuse and the first programmable element is programmed by blowing the fuse. 
     
     
       21. The control circuit of claim 20, wherein the first programmable element is programmed by a power-on reset signal. 
     
     
       22. The control circuit of claim 11, wherein the control circuitry further comprises: a first programmable element having an output signal that is gated with an output signal of the first logic element to produce the first speed grade signal, wherein the first programmable element is capable of being programmed to speed up the first speed grade signal.   
     
     
       23. The control circuit of claim 22, wherein the first programmable element is a fuse and the first programmable element is programmed by blowing the fuse. 
     
     
       24. The control circuit of claim 23, wherein the first programmable element is programmed by blowing the fuse. 
     
     
       25. The control circuit of claim 11, wherein the control circuitry further comprises: a delay element that delays an output signal of the third logic element to generate a delayed signal; and   a fourth logic element that receives the output signal of the third logic element as a first input signal and the delayed signal generated by the delay element as a second input signal and that generates the control output signal.   
     
     
       26. The control circuit of claim 11, wherein the control circuitry further comprises: a plurality of block reset control circuits, with each block reset control circuit of the plurality of block reset control circuits associated with a block of a plurality of blocks of the synchronous integrated circuit memory device, wherein each block reset control circuit receives the control output signal as a first input signal and a second signal as a second input signal, and wherein a selected block reset control circuit generates a reset signal that terminates the write pulse of the selected block reset control circuit; and   wherein during the test mode of the synchronous integrated circuit memory device, the control output signal controls the reset signal that terminates the write pulse of the selected block reset control signal.   
     
     
       27. The control circuit of claim 26, wherein the block control reset circuit receives the first speed grade signal as a third input signal and the first speed grade signal is capable of speeding up termination of the write pulse of the block reset control signal. 
     
     
       28. The control circuit of claim 26, wherein the block control reset circuit receives a sense amplifier enable signal as a third input signal and during the normal mode of the synchronous integrated circuit memory device, the second signal and the sense amplifier enable signal control the reset signal that terminates the write pulse of the block reset control circuit. 
     
     
       29. The control circuit of claim 26, wherein during a normal mode of the synchronous integrated circuit memory device, the second signal controls the reset signal that terminates the write pulse of the block reset control circuit. 
     
     
       30. The control circuit of claim 11, wherein the external control signal is the clock signal or a derivative signal of the clock signal. 
     
     
       31. The control circuit of claim 11, wherein during a normal operating mode, the synchronous integrated circuit memory device is internally self-timed.