Cold cathode field emission display and method for forming it

Abstract

A cold cathode field emission display is described. A key feature of its design is that each group of microtips that constitute a pixel is located on the same equipotential surface and a reliable ballast resistor is interposed between the equipotential surface and the cathode line which powers the pixel. An efficient method for manufacturing the display is also described.

What is claimed is: 
     
       1. A cold cathode field emission display comprising: an insulating substrate;   a plurality of thin film serpentine resistors on said substrate, each resistor having a first end and a second end and a resistance between about 50 megohm and 500 megohms;   cathode columns for said display, formed of parallel spaced conductors on said substrate, contacting the first end of a resistor;   a plurality of equipotential areas on said substrate, each contacting the second end of a resistor;   a dielectric layer on said cathode columns and said equipotential areas;   gate lines on said dielectric layer, formed of parallel spaced conductors, over, and at right angles to, said cathode columns and overlapping said equipotential areas;   a plurality of openings, located at the overlaps of said equipotential areas and said gate lines, passing through said gate lines and through said dielectric layer; and   a plurality of groups of cone shaped field emission microtips, each group being in contact with the same equipotential area and each microtip being centrally located within one of the openings, the base of each of said microtips being in contact with one of said equipotential areas and the apex of each microtip being in the same plane as that of said gate lines.   
     
     
       2. The field emission display of claim 1 wherein the material that comprises the thin film resistors is taken from the group consisting of silicon and indium tin oxide. 
     
     
       3. The field emission display of claim 1 wherein said dielectric comprises material taken from the group consisting of silicon oxide and silicon nitride. 
     
     
       4. The field emission display of claim 1 wherein said cathode columns and equipotential areas comprise material taken from the group consisting of aluminum, molybdenum, niobium, tungsten, and polysilicon. 
     
     
       5. The field emission display of claim 1 wherein said gate lines comprise material taken from the group consisting of aluminum, molybdenum, niobium, tungsten, and polysilicon. 
     
     
       6. The field emission display of claim 1 wherein the distance between said first and second ends of one of the resistors is less than about 10 microns. 
     
     
       7. A method for manufacturing a cold cathode field emission display, comprising: providing a dielectric substrate;   depositing a layer of electrically resistive material, having a sheet resistance between about 1 and 100 megohms per square, onto one surface of said substrate;   patterning and etching said resistive layer to form a plurality of serpentine thin film resistors;   depositing a first layer of electrically conductive material on said layer of electrically resistive material and patterning and etching said first conductive layer to form cathode columns and equipotential areas;   depositing a dielectric layer on said first conductive layer;   depositing a second electrically conductive layer on said dielectric layer and patterning said second conductive layer to form gate lines;   forming openings in said gate lines and said dielectric layer at the overlaps of the equipotential areas and the gate lines, down to the level of the equipotential areas; and   forming a plurality of groups of cone shaped field emission microtips, each group sharing the same equipotential area and each microtip being centrally located within one of the openings, the base of each of said microtips being in contact with an equipotential area and the apex of each microtip being in the same plane as that of said gate lines.   
     
     
       8. The method of claim 7 wherein said resistive layer comprises material taken from the group consisting of silicon and indium tin oxide. 
     
     
       9. The method of claim 7 wherein the thickness of said resistive layer is between about 1,000 and 4,500 Angstrom units. 
     
     
       10. The method of claim 7 wherein the thickness of said dielectric layer is between about 10,500 and 15,000 Angstrom units. 
     
     
       11. The method of claim 7 wherein the thickness of said first conductive layer is between about 2,000 and 5,000 Angstrom units. 
     
     
       12. The method of claim 7 wherein the thickness of said second conductive layer is between about 2,000 and 5,000 Angstrom units.