Semiconductor memory

Abstract

In the semiconductor memory of this invention, a first unit of data that is inputted by means of the same standard clock as an external address and that is inputted to a chip prior to determination of the internal address signal that is prefetched is latched to all latch circuits into which this data may be latched. After an address is determined by the next standard clock, second and succeeding units of data inputted to the chip are inputted only to latch circuits that are latched in accordance with address signals. In this way, even if internal address signal processing has not been completed at the time of latching the first unit of data, both the first unit of data and second and succeeding units of data can be latched in prefetch circuits designated by addresses from the outside.

What is claimed is: 
     
       1. A write method for a semiconductor memory having an internal address generating circuit, a data buffer, a latch pulse generating circuit, a first data latch circuit, and a second data latch circuit, comprising: said internal address generating circuit generating an internal address signal in response to an external address signal, said data buffer receiving at least first and second data, said latch pulse generating circuit generating first and second pulse signals, controlling said first data latch circuit in response to said first pulse signal, and controlling said second data latch circuit in response to said second pulse signal,   said latch pulse generating circuit generating said first and second pulse signals in response to said external address signal, said first and second data latch circuits latching said first data from said data buffer in response to said first and second pulse signals respectively, said latch pulse generating circuit continuously generating said first pulse signal in response to said internal address signal, and said first data latch circuit latching said second data from said data buffer in response to said first pulse signal.   
     
     
       2. A semiconductor memory comprising: an internal address generating circuit generating an internal address signal in response to an external address signal;   a data buffer receiving at least first and second data;   a latch pulse generating circuit generating first and second pulse signals;   a first data latch circuit controlled by said first pulse signal; and   a second data latch circuit controlled by said second pulse signal;   said latch pulse generating circuit generating said first and second pulse signals in response to said external address signal, said first and second data latch circuits latch said first data from said data buffer in response to said first and second pulse signals, respectively, said latch pulse generating circuit continuously generating said first pulse signal in response to said internal address signal, and said first data latch circuit latching said second data from said data buffer in response to said first pulse signal.   
     
     
       3. A write method for a semiconductor memory having an internal address generating circuit, a data buffer, first and second data latch circuits, and a latch pulse generating circuit, comprising: said internal address generating circuit generating an internal address signal receiving at least first and second data,   said latch pulse generating circuit generating a first pulse signal in response to said external address signal, said first and second data latch circuits latching said first data from said data buffer in response to said first pulse signal, said latch pulse generating circuit continuously generating a second pulse signal selecting said first data latch circuit in response to said internal address signal, and said first data latch circuit latching said second data from said data buffer in response to said second pulse signal.   
     
     
       4. A semiconductor memory comprising: an internal address generating circuit generating an internal address signal in response to an external address signal;   a data buffer receiving at least first and second data;   a latch pulse generating circuit generating a first pulse signal in response to said external address signal; and   first and second data latch circuits latching said first data from said data buffer in response to said first pulse signal;   said latch pulse generating circuit continuously generating a second pulse signal selecting said first data latch circuit in response to said internal address signal, and said first data latch circuit latching said second data from said data buffer in response to said second pulse signal.