High speed variable length code decoder

Abstract

A high speed variable length code (VLC) decoder for decoding in real time data encoded in a system such as MPEG 1, MPEG 2 or HDTV (high definition television) includes a bit stream buffer, a data buffer, a pair of latch units, a pair of selectors, a barrel shifter, a VLC table random logic, an output buffer, an accumulator, and a VLC decoder controller. The VLC decoder controller appropriately controls data flow in the VLC decoder, by using a bit empty signal from the bit stream signal, a data empty signal from the data buffer, a data full signal from the output buffer and a carry signal from the accumulator.

What is claimed is: 
     
       1. A high speed variable length code (VLC) decoder, comprising: a bit stream buffer for storing therein an externally applied variable bit stream data, configuring the stored data into 32-bit parallel data, and outputting therefrom the configured data, but outputting therefrom a bit empty signal when there is no data stored therein;   a data buffer for sequentially storing therein 32-bit data applied thereto from the bit stream buffer in accordance with a read signal but outputting therefrom a bit empty signal when there is no data stored therein;   a first latch unit for temporarily storing therein the data applied thereto from the data buffer and outputting therefrom the stored data in accordance with the read signal;   a first selector for outputting therefrom the data applied thereto from the first latch unit in accordance with the read signal;   a barrel shifter for outputting therefrom a certain number of bits stored therein, after being shifted by a shift signal;   a second latch unit for temporarily storing the data applied thereto from the barrel shifter and outputting therefrom the stored data in accordance with an internal control signal;   a VLC table random logic for decoding the data applied thereto from the second latch unit and outputting a code word and a bit length value in the code word;   an output buffer for storing and outputting therefrom the value applied thereto from the VLC table random logic, or outputting therefrom a data full signal when full of data;   a second selector selectively outputting therefrom a bit length value applied thereto from the VLC table random logic and a ready-set value "0", each in accordance with the read signal;   an accumulator for receiving the value applied thereto from the second selector, generating the read signal and transmitting a shift signal to the barrel shifter; and   a VLC decoder controller for receiving the read signal, the bit empty signal, the data empty signal and the data full signal, respectively, and outputting an internal control signal to each of the accumulator and the second latch for properly controlling the data flow.   
     
     
       2. The decoder of claim 1, wherein the first latch unit comprises a first latch for temporarily storing a data applied thereto from the data buffer and outputting therefrom the stored data, and a second latch for temporarily storing therein the data applied thereto from the first latch in accordance with the read signal and outputting therefrom the stored data. 
     
     
       3. The decoder of claim 2, wherein the first and second latches each have a capacity equivalent to the value of the longest code word length. 
     
     
       4. The decoder of claim 1, wherein the first selector includes a first selection circuit for selectively outputting the data applied thereto from each of the data buffer and the first latch in accordance with the read signal, and a second selection circuit for selectively outputting therefrom the data applied thereto from the first and second latches in accordance with the read signal. 
     
     
       5. The decoder of claim 4, wherein the first selector is composed of a pair of multiplexors. 
     
     
       6. The decoder of claim 1, wherein the barrel shifter provided with a 32-bit slide window which is shifted therein by the shift signal transmits to the second latch unit the data applied thereto from the first selector and selected by the slide window. 
     
     
       7. The decoder of claim 1, wherein the second latch unit temporarily stores therein and outputs therefrom the data applied thereto from the barrel shifter in accordance with the internal control signal outputted from the VLC decoder controller. 
     
     
       8. The decoder of claim 1, wherein the VLC table random logic decodes one code word among the data applied thereto from the second latch unit, and outputs the decoded code word value, which is in turn transmitted to each of the output buffer and the second selector or controls another external block. 
     
     
       9. The decoder of claim 1, wherein the output buffer stores therein and outputs therefrom the data decoded in the VLC table random logic, and transmits the data full signal to the VLC decoder controller when it is full of data. 
     
     
       10. The decoder of claim 1, wherein the second selector is composed of a multiplexor. 
     
     
       11. The decoder of claim 1, wherein the accumulator includes an adder for adding to a previous residue value the value of the data applied thereto selectively from the second selector when a bit length value of a present code word in the second selector is applied thereto, a residue latch for storing therein the previous residue value, and a carry latch for generating and outputting to each of the data buffer and the latch unit the read signal in accordance with a carry value outputted from the adder and an externally applied clock signal. 
     
     
       12. The decoder of claim 1, wherein the VLC decoder controller is composed of multiple combined logic and controls the operation of the VLC decoder. 
     
     
       13. The decoder of claim 1, wherein the barrel shifter transmits to the VLC table random logic a 32-bit data outputted from the first latch unit and allocated by a slide window. 
     
     
       14. The decoder of claim 13, wherein the shifting by the slide window is decided by a signal outputted from the accumulator.