Interactive circuit designing apparatus

Abstract

The invention provides an interactive circuit designing apparatus wherein a logic design, a layout design and a speed analysis can cooperate with each other in processing. The interactive circuit designing apparatus comprises a logical designing section for logically designing a design object circuit, a layout designing section for performing mounting arrangement of logical components constituting a design object circuit based on a result of the logical design and performing wiring between the logical components, and a speed analysis section for performing a speed analysis based on calculation of a delay for each of paths on the design object circuit in accordance with a result of the layout. The logical designing section, the layout designing section and the speed analysis section are connected to each other so as to cooperate with each other when necessary. The interactive circuit designing apparatus is applied to an apparatus for designing a circuit of an LSI, a printed circuit board or a like element.

What is claimed is: 
     
       1. An interactive circuit designing apparatus, comprising: a display section for displaying a process of a circuit design to allow a circuit design to be performed interactively;   an inputting section for inputting response information to display data displayed on said display section;   logical designing means for logically designing a design object circuit;   layout designing means for performing a mounting arrangement of logical components constituting the design object circuit based on a result of the logical design by said logical designing means and performing a wiring between the logical components;   speed analysis means for performing a speed analysis based on a calculation of a delay for each of a plurality of paths on the design object circuit in accordance with a result of the design by said layout designing means; and   a grouping section for grouping, after a plurality of logical components to which a predetermined signal is to be distributed are arranged for mounting by said layout designing means, the plurality of logical components for last stage temporary positions of a signal distribution circuit for distributing the signal, and wherein said logical designing means includes a logic circuit addition section for generating a signal distribution circuit for distributing a signal from a signal source to the individual logical components based on the last state temporary positions and the plurality of logical component groups obtained by grouping by said grouping section and adding the signal distribution circuit as a logic circuit, said layout designing means determining a mounting arrangement of the signal distribution circuit based on the logic circuit as the signal distribution circuit added by said logic circuit addition section;   said logical designing means, said layout designing means and said speed analysis means being connected to each other so as to cooperate with each other.   
     
     
       2. The interactive circuit designing apparatus as claimed in claim 1, wherein the last stage temporary positions and the plurality of logical component groups obtained by grouping by said grouping section are displayed on said display section. 
     
     
       3. The interactive circuit designing apparatus as claimed in claim 2, wherein estimated wiring line lengths from the last stage temporary positions to the individual logical components are displayed on said display section. 
     
     
       4. The interactive circuit designing apparatus as claimed in claim 3, further comprising a grouping variation acceptance section for accepting a request for variation of the grouping inputted from said inputting section in response to the display of said display section and requesting said grouping section for variation of the grouping. 
     
     
       5. The interactive circuit designing apparatus as claimed in claim 4, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       6. The interactive circuit designing apparatus as claimed in claim 4, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       7. The interactive circuit designing apparatus as claimed in claim 3, further comprising a signal distribution circuit last stage arrangement variation acceptance section for accepting a request for variation of the last stage temporary positions inputted from said inputting section in response to the display of said display section and developing a request for variation of the last stage temporary positions. 
     
     
       8. The interactive circuit designing apparatus as claimed in claim 7, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       9. The interactive circuit designing apparatus as claimed in claim 7, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       10. The interactive circuit designing apparatus as claimed in claim 3, further comprising a logical component arrangement variation acceptance section for accepting a request for variation of an arrangement position of a logical component inputted from said inputting section in response to the display of said display section and requesting said layout designing means for variation of the arrangement position of the logical component. 
     
     
       11. The interactive circuit designing apparatus as claimed in claim 10, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       12. The interactive circuit designing apparatus as claimed in claim 10, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       13. The interactive circuit designing apparatus as claimed in claim 3, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       14. The interactive circuit designing apparatus as claimed in claim 3, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       15. The interactive circuit designing apparatus as claimed in claim 2, further comprising a grouping variation acceptance section for accepting a request for variation of the grouping inputted from said inputting section in response to the display of said display section and requesting said grouping section for variation of the grouping. 
     
     
       16. The interactive circuit designing apparatus as claimed in claim 15, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       17. The interactive circuit designing apparatus as claimed in claim 15, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       18. The interactive circuit designing apparatus as claimed in claim 2, further comprising a signal distribution circuit last stage arrangement variation acceptance section for accepting a request for variation of the last stage temporary positions inputted from said inputting section in response to the display of said display section and developing a request for variation of the last stage temporary positions. 
     
     
       19. The interactive circuit designing apparatus as claimed in claim 18, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       20. The interactive circuit designing apparatus as claimed in claim 18, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       21. The interactive circuit designing apparatus as claimed in claim 2, further comprising a logical component arrangement variation acceptance section for accepting a request for variation of an arrangement position of a logical component inputted from said inputting section in response to the display of said display section and requesting said layout designing means for variation of the arrangement position of the logical component. 
     
     
       22. The interactive circuit designing apparatus as claimed in claim 21, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       23. The interactive circuit designing apparatus as claimed in claim 21, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       24. The interactive circuit designing apparatus as claimed in claim 2, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       25. The interactive circuit designing apparatus as claimed in claim 2, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       26. The interactive circuit designing apparatus as claimed in claim 1, wherein the signal distribution circuit added by said logic circuit addition section is displayed on said display section. 
     
     
       27. The interactive circuit designing apparatus as claimed in claim 26, further comprising an additional circuit variation acceptance section for accepting a request for variation of the signal distribution circuit inputted from said inputting section in response to the display of said display section and requesting said logic circuit addition section for variation of the signal distribution circuit. 
     
     
       28. The interactive circuit designing apparatus as claimed in claim 27, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       29. The interactive circuit designing apparatus as claimed in claim 27, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       30. The interactive circuit designing apparatus as claimed in claim 26, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       31. The interactive circuit designing apparatus as claimed in claim 26, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       32. The interactive circuit designing apparatus as claimed in claim 1, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a clock signal. 
     
     
       33. The interactive circuit designing apparatus as claimed in claim 1, wherein the predetermined signal distributed to the logical components by said signal distribution circuit is a reset signal. 
     
     
       34. The interactive circuit designing apparatus as claimed in claim 1, wherein said logical designing means includes a construction information decision section for deciding, after a plurality of logical components to be diagnosed are arranged for mounting by said layout designing means, construction information of a diagnosis facilitation circuit for diagnosing the plurality of logical components based on a result of arrangement of the plurality of logical components, and said layout designing means performs mounting arrangement of the diagnosis facilitation circuit based on the construction information of the diagnosis facilitation circuit decided by said construction information decision section. 
     
     
       35. The interactive circuit designing apparatus as claimed in claim 34, wherein the construction information of the diagnosis facilitation circuit decided by said construction information decision section is displayed on said display section. 
     
     
       36. The interactive circuit designing apparatus as claimed in claim 35, further comprising a construction information variation acceptance section for accepting a request for variation of the construction information inputted from said inputting section in response to the display of said display section and requesting said construction information decision section for variation of the construction information. 
     
     
       37. The interactive circuit designing apparatus as claimed in claim 36, wherein said construction information decision section decides, where the diagnosis facilitation circuit is of the scan chain type, a connection order of the plurality of logical components as the construction information for constructing a scan chain. 
     
     
       38. The interactive circuit designing apparatus as claimed in claim 36, wherein said construction information decision section decides, where the diagnosis facilitation circuit is of the address scan type, addresses for scanning the logical components as the construction information. 
     
     
       39. The interactive circuit designing apparatus as claimed in claim 35, wherein said construction information decision section decides, where the diagnosis facilitation circuit is of the scan chain type, a connection order of the plurality of logical components as the construction information for constructing a scan chain. 
     
     
       40. The interactive circuit designing apparatus as claimed in claim 35, wherein said construction information decision section decides, where the diagnosis facilitation circuit is of the address scan type, addresses for scanning the logical components as the construction information. 
     
     
       41. The interactive circuit designing apparatus as claimed in claim 34, wherein said construction information decision section decides, where the diagnosis facilitation circuit is of the scan chain type, a connection order of the plurality of logical components as the construction information for constructing a scan chain. 
     
     
       42. The interactive circuit designing apparatus as claimed in claim 34, wherein said construction information decision section decides, where the diagnosis facilitation circuit is of the address scan type, addresses for scanning the logical components as the construction information. 
     
     
       43. The interactive circuit designing apparatus as claimed in claim 1, further comprising a temporary wiring line production section for imaginatively wiring, after a mounting arrangement of the logical components is decided by said layout designing means, the logical components, and a confusion degree calculation section for calculating a confusion degree of wiring lines on the design object circuit based on a result of the temporary wiring by said temporary wiring line production section, the confusion degree calculated by said confusion degree calculation section being displayed on said display section. 
     
     
       44. The interactive circuit designing apparatus as claimed in claim 43, wherein said confusion degree calculation section divides the design object circuit into a plurality of grating-like areas and calculates, for each wiring layer of the design object circuit, a ratio of the number of estimated used channels based on a result of the temporary wiring by said temporary wiring line production section to the number of usable channels in each of the gratings as the confusion degree. 
     
     
       45. The interactive circuit designing apparatus as claimed in claim 44, further comprising a logical component arrangement variation acceptance section for accepting a request for variation of the mounting arrangement of a logical component inputted from said inputting section in response to the display of said display section and requesting said layout designing means for variation of the mounting arrangement. 
     
     
       46. The interactive circuit designing apparatus as claimed in claim 44, wherein said confusion degree calculation section calculates, after mounting wiring of the logical components is decided by said layout designing means, the confusion degree based on a result of the mounting wiring, the confusion degree calculated by said confusion degree calculation section being displayed on said display section. 
     
     
       47. The interactive circuit designing apparatus as claimed in claim 43, wherein said confusion degree calculation section calculates the number of free channels at a coordinate of each wiring layer in the direction of a main wiring line as the confusion degree. 
     
     
       48. The interactive circuit designing apparatus as claimed in claim 47, further comprising a logical component arrangement variation acceptance section for accepting a request for variation of the mounting arrangement of a logical component inputted from said inputting section in response to the display of said display section and requesting said layout designing means for variation of the mounting arrangement. 
     
     
       49. The interactive circuit designing apparatus as claimed in claim 47, wherein said confusion degree calculation section calculates, after mounting wiring of the logical components is decided by said layout designing means, the confusion degree based on a result of the mounting wiring, the confusion degree calculated by said confusion degree calculation section being displayed on said display section. 
     
     
       50. The interactive circuit designing apparatus as claimed in claim 43, further comprising a logical component arrangement variation acceptance section for accepting a request for variation of the mounting arrangement of a logical component inputted from said inputting section in response to the display of said display section and requesting said layout designing means for variation of the mounting arrangement. 
     
     
       51. The interactive circuit designing apparatus as claimed in claim 43, wherein said confusion degree calculation section calculates, after mounting wiring of the logical components is decided by said layout designing means, the confusion degree based on a result of the mounting wiring, the confusion degree calculated by said confusion degree calculation section being displayed on said display section. 
     
     
       52. The interactive circuit designing apparatus as claimed in claim 1, wherein, when a mounting arrangement of the logical components is decided by said layout designing means, an arrangement map of the design object circuit on which the logical components are arranged and a logical component list of the logical components to be arranged on said arrangement map are displayed in response to an instruction from said inputting section on said display section. 
     
     
       53. The interactive circuit designing apparatus as claimed in claim 52, further comprising a logical component arrangement section for arranging on said arrangement map a logical component selected on said logical component list in response to an instruction from said inputting section. 
     
     
       54. The interactive circuit designing apparatus as claimed in claim 53, further comprising a logical component deletion section for deleting from said arrangement map a logical component selected on said logical component list or said arrangement map in response to an instruction from said inputting section. 
     
     
       55. The interactive circuit designing apparatus as claimed in claim 53, further comprising a logical component movement section for moving a logical component selected on said logical component list or said arrangement map to another position on said arrangement map in response to an instruction from said inputting section. 
     
     
       56. The interactive circuit designing apparatus as claimed in claim 53, further comprising an information retrieval section for searching individual information or connection information of a logical component selected on said logical component list or said arrangement map in response to an instruction from said inputting section and causing the individual information or connection information thus searched out to be displayed on said display section. 
     
     
       57. The interactive circuit designing apparatus as claimed in claim 56, wherein a connection information list between a selected logical component and all logical components connected to the selected logical component is displayed as the connection information. 
     
     
       58. The interactive circuit designing apparatus as claimed in claim 57, wherein the connection information list includes logical lengths between the selected logical component and all logical components connected to the selected logical component. 
     
     
       59. The interactive circuit designing apparatus as claimed in claim 58, wherein, when any of the logical lengths violates a predetermined rule, the displaying condition of that portion of the connection information including the logical length which violates the rule is changed over into a visually identifiable condition on said connection information list. 
     
     
       60. The interactive circuit designing apparatus as claimed in claim 53, further comprising a catalogue arrangement section for storing a basic arrangement pattern for arranging a plurality of logical components in a same arrangement as a catalogue and repetitively arranging the basic arrangement pattern on said arrangement map in response to an instruction from said inputting section. 
     
     
       61. The interactive circuit designing apparatus as claimed in claim 60, wherein, when a plurality of logical components are arranged on said arrangement map by said logical component arrangement section, the logical components are simultaneously stored as the basic arrangement pattern. 
     
     
       62. The interactive circuit designing apparatus as claimed in claim 60, wherein a plurality of logical components selected on said arrangement map and arranged already are stored as the basic arrangement pattern in response to an instruction from said inputting section. 
     
     
       63. The interactive circuit designing apparatus as claimed in claim 1, further comprising an external file writing section for writing, during execution of mounting arrangement of the logical components by said layout designing means, data of the arrangement in a text form into an external file. 
     
     
       64. The interactive circuit designing apparatus as claimed in claim 1, wherein, immediately after mounting arrangement processing of the logical components by said layout designing means, a speed analysis by said speed analysis means is performed based on a temporary wiring line length between the logical components according to the mounting arrangement, and the mounting arrangement of the logical components is varied in response to a result of the speed analysis by said layout designing means. 
     
     
       65. The interactive circuit designing apparatus as claimed in claim 1, wherein, immediately after wiring processing of the logical components by said layout designing means, a speed analysis by said speed analysis means is performed based on an actual wiring line length by the wiring, and the wiring of the logical components is varied in response to a result of the speed analysis by said layout designing means. 
     
     
       66. The interactive circuit designing apparatus as claimed in claim 1, further comprising a path tracing section for tracing a wiring line path connected to a pin of a logical component designated by an instruction from said inputting section upon execution of a speed analysis by said speed analysis means from the pin, and a path delay display control section for controlling said display section to display thereon a result of a delay calculation of the wiring line path traced by said path tracing section as a path delay list. 
     
     
       67. The interactive circuit designing apparatus as claimed in claim 66, further comprising a route map display control section for controlling said display section to display thereon a route of a wiring line path designated on the path display list and delays and waveforms at pins on the wiring line path as a route map in response to an instruction from said inputting section. 
     
     
       68. The interactive circuit designing apparatus as claimed in claim 67, further comprising a mounting data display control section for controlling said display section to emphatically display thereon a mounting arrangement condition and a wiring condition of a gate or a network designated on the route map in response to an instruction from said inputting section. 
     
     
       69. The interactive circuit designing apparatus as claimed in claim 1, further comprising a wiring line parasitic capacitance coding section for coding, upon wiring processing between the logical components by said layout designing means, wiring line parasitic capacitances on the design object circuit according to an arrangement and a wiring scheme decided by said layout designing means at present, and a wiring line parasitic capacitance code display control section for controlling said display section to display thereon code information obtained by coding by said wiring line parasitic capacitance coding section in a superimposed relationship on the arrangement map of the design object circuit on said display section.