Voltage generator for electrically programmable non-volatile memory cells

Abstract

A voltage generator for electrically programmable non-volatile memory cells, constructed of a number of charge pump circuits having inputs controlled by a number of phase generators. The charge pump circuits are laid as pairs of first and second charge pump circuits. The first charge pump circuits are active when the second charge pump circuits are inactive, and vice versa.

We claim: 
     
       1. A voltage generator for electrically programmable non-volatile memory cells, comprising: a plurality of charge pump circuits, each of which has respective inputs and an output, the inputs being controlled by a respective plurality of phase generators, and the output being connected to an output terminal of the voltage generator; and   wherein the plurality of charge pump circuits are grouped in pairs of first and second charge pump circuits, the first charge pump circuits being active while the second charge pump circuits are inactive, and the second charge pump circuits being active while the first charge pump circuits are inactive.   
     
     
       2. A voltage generator according to claim 1 wherein each of the phase generators are connected to a respective plurality of the charge pump circuits through a bus to supply a plurality of phase signals, the phase signals having the same frequency and being shifted in phase from each other by a selected increment, the phase signals being supplied to control the pairs of first and second charge pump circuits, each first charge pump circuit being controlled in opposition to each respective second charge pump circuit. 
     
     
       3. A voltage generator according to claim 2 wherein the plurality of phase generators are connected to a clock generator circuit, the clock generator circuit receiving a control signal and outputting a plurality of clock signals having the same frequency and being shifted in phase from each other by a selected increment. 
     
     
       4. A voltage generator according to claim 2, further comprising a voltage limiter circuit having an input and an output, the input being connected to the output terminal of the voltage generator, the output being connected to each of the plurality of charge pump circuits; and wherein the voltage limiter circuit further receives a control signal and a programming voltage signal for programming the memory cells.   
     
     
       5. A voltage generator according to claim 1, further comprising at least four pairs of the charge pump circuits being connected to respective ones of the plurality of phase generators, wherein each first charge pump circuit receives first, second, and third phase signals and each second charge pump circuit receives the first and third phase signals and a fourth phase signal; and wherein each of the first, second, third, and fourth phase signals is of the same frequency and is shifted in phase from the other phase signals by one eighth of the period of the phase signals.   
     
     
       6. A phase generator for a programming circuit for a matrix array of electrically programmable non-volatile memory cells, comprising an input terminal and first, second, third, and fourth output terminals, the input terminal being connected to the output terminals through first and second input logic converters and, respectively, first, second, third, and fourth circuit legs, the respective circuit legs producing first, second, third, and fourth feedback signals. 
     
     
       7. A charge pump circuit for a programming circuit for a matrix array of electrically programmable non-volatile memory cells comprising at least first, second, and third input terminals receiving respective phase signals from a phase generator, the input terminals being connected to an output terminal of the charge pump circuit through first, second, and third pump capacitors, respectively. 
     
     
       8. A voltage generator for electrically programmable non-volatile memory cells comprising: a plurality of charge pump circuits arranged in pairs of first and second charge pump circuits, an output node of each charge pump circuit being connected to an output terminal of the voltage generator; and   wherein each pair of first and second charge pump circuits receives a set of phase signals, wherein each pair of first and second charge pump circuits is controlled by the phase signals whereby each first charge pump circuit is active while the corresponding second charge pump circuit is inactive, and each second charge pump circuit is active while the corresponding first charge pump circuit is inactive.   
     
     
       9. A voltage generator according to claim 8 wherein each phase signal has the same frequency and is shifted in phase by a selected increment with respect to every other phase signal. 
     
     
       10. A voltage generator according to claim 9 wherein each first charge pump circuit receives first, second, and third phase signals wherein each second charge pump circuit receives the first and third phase signals and a fourth phase signal. 
     
     
       11. A voltage generator for electrically programmable non-volatile memory cells, comprising a plurality of charge pump circuits having their inputs controlled by a plurality of phase generators and their outputs connected to an output terminal of the voltage generator, wherein said charge pump circuits are laid as pairs of first and second charge pump circuits, the first charge pump circuits being active while the second charge pump circuits are inactive, and vice versa. 
     
     
       12. A voltage generator according to claim 11 wherein each of said phase generators, connected to said charge pump circuits through a bus, supplies a plurality of phase signals, having the same frequency and being shifted in phase from each other by a suitable amount, for controlling in opposition phase the pairs of charge pump circuits. 
     
     
       13. A voltage generator according to claim 12 wherein said phase generators are connected to a clock generator circuit being input a control signal and outputting a plurality of clock signals with the same frequency and shifted in phase from each other by a suitable amount. 
     
     
       14. A voltage generator according to claim 11, further comprising a voltage limiter circuit having an input connected to the output terminal of the voltage generator and an output connected to the charge pump circuits, said voltage limiter circuit being input a control signal and a programming voltage signal for programming the memory cells. 
     
     
       15. A voltage generator according to claim 11, further comprising at least four pairs of charge pump circuits connected to respective phase generators, each first charge pump circuit being input first, second and third phase signals, each second charge pump circuit being input a fourth phase signal and said first and third phase signals, said phase signals being shifted in phase from each other by one eighth of a period. 
     
     
       16. A voltage generator according to claim 11 wherein each of said charge pump circuits includes at least first, second and third input terminals receiving respective phase signals from one of the phase generators, said circuits being connected to an output terminal through first, second and third pump capacitors. 
     
     
       17. A voltage generator according to claim 16 wherein said first input terminal is connected to said first pump capacitor through an enabling circuit comprising first and second transistors connected, in parallel with each other, between the first pump capacitor, the first input terminal and a ground voltage reference of the charge pump circuit, the control terminals of said transistors including first and second enabling terminals of the enabling circuit respectively receiving first and second enabling signals which are complementary of each other. 
     
     
       18. A voltage generator according to claim 16 wherein said second and third pump capacitors are connected to the output terminal of the charge pump circuit through a decoupling circuit comprising first, second and third MOS transistors. 
     
     
       19. A voltage generator according to claim 13 wherein said clock generator circuit comprises a loop of a plurality of primary inverters and secondary inverters which supply, on a plurality of outputs, said clock signals, each of said primary inverters having an input terminal connected to an output terminal of a secondary inverter preceding it in the loop and to a ground voltage reference, through a MOS transistor controlled by a secondary control signal which corresponds to the negated control signal, in parallel with a capacitor, and having an output terminal connected to a first input of the secondary inverter lying next to it in the loop, and to one of the outputs. 
     
     
       20. A voltage generator according to claim 11 wherein said first, second and third pump capacitors comprise three-terminal capacitors in a parallel type of connection. 
     
     
       21. A charge pump circuit for a programming circuit of a matrix array of electrically programmable non-volatile memory cells, comprising at least first, second and third input terminals receiving respective phase signals from a phase generator, wherein said input terminals are connected to an output terminal of the charge pump circuit through first, second and third pump capacitors, respectively. 
     
     
       22. A charge pump circuit according to claim 21 wherein said first input terminal is connected to said first pump capacitor through an enabling circuit which comprises first and second MOS transistors connected, in parallel with each other, between the first pump capacitor and respectively the first input terminal and a ground voltage reference, the control terminals of said transistors including first and second enabling terminals of the enabling circuit and receiving first and second enabling signals which are complementary of each other. 
     
     
       23. A charge pump circuit according to claim 21 wherein said second and third pump capacitors are connected to the output terminal through a decoupling circuit comprising first, second and third MOS transistors, the first transistor having its control and drain terminals connected together and to the source terminal of the second transistor, as well as to the source terminal of the third transistor and to the second pump capacitor, and having its source terminal connected to the drain terminal of the second transistor and to the control terminal of the third transistor, as well as to the third pump capacitor, and the second transistor also having its control terminal connected to the drain terminal of the third transistor, in turn connected to the output terminal of the charge pump circuit. 
     
     
       24. A phase generator for a programming circuit of a matrix array of electrically programmable non-volatile memory cells, comprising an input terminal and first, second, third and fourth output terminals, wherein said input terminal is connected to said output terminals respectively through a series of first and second input logic inverters and respectively first, second, third and fourth circuit legs outputting first, second, third and fourth feedback signals. 
     
     
       25. A phase generator according to claim 24, further comprising first, second, third and fourth output logic inverters connected between said circuit legs and respective output terminals of the phase generator. 
     
     
       26. A phase generator according to claim 24 wherein said first feedback signal supplies the second circuit leg, said second feedback signal supplies, through a first feedback logic inverter, the first circuit leg, and, through a second feedback logic inverter, the fourth circuit leg, said third feedback signal supplies, through a third feedback logic inverter, the fourth circuit leg, and said fourth feedback signal supplies the second and third circuit legs. 
     
     
       27. A clock generator circuit for a programming circuit of a matrix array of electrically programmable non-volatile memory cells, comprising a loop of a plurality of primary inverters and secondary inverters supplying clock signals on a plurality of outputs, each of said primary inverters having an input terminal connected to an output terminal of a secondary inverter preceding it in the loop, and to a ground voltage reference through a MOS transistor controlled by a secondary control signal which corresponds to a negated control signal, in parallel with a capacitor, and having an output terminal connected to a first input of the secondary inverter lying next to it in the loop, and to one of the outputs. 
     
     
       28. A clock generator circuit according to claim 27 wherein said loop further comprises a logic gate of the NAND type having a first input connected to the output terminal of one of the primary inverters and an output connected to said first input of one of the secondary inverters, said logic gate being input the control signal, each of said secondary inverters having second and third input terminals which receive a pair of reference signals being generated by a reference circuit and complementary of each other. 
     
     
       29. A charge pump circuit according to claim 21, characterized in that said first, second and third pump capacitors are three-terminal capacitors in a parallel type of connection. 
     
     
       30. A programming circuit for a matrix array of electrically programmable non-volatile memory cells, comprising at least one voltage regulator as claimed in claim 11. 
     
     
       31. A programming circuit for a matrix array of electrically programmable non-volatile memory cells, comprising at least one charge pump circuit as claimed in claim 21. 
     
     
       32. A programming circuit for a matrix array of electrically programmable non-volatile memory cells, comprising at least one phase generator as claimed in claim 24. 
     
     
       33. A programming circuit for a matrix array of electrically programmable non-volatile memory cells, comprising at least one clock generator circuit as claimed in claim 27. 
     
     
       34. A method for supplying voltage to electrically programmable non-volatile memory cells, comprising the steps of: activating a plurality of first charge pump circuits and deactivating a respective plurality of second charge pump circuits during a first selected period of time; and   deactivating the plurality of first charge pump circuits and activating the respective plurality of second charge pump circuits during a second selected period of time.   
     
     
       35. A method according to claim 34, further comprising the step of generating a plurality of phase signals to control the activation and deactivation of the plurality of first charge pump circuits and the respective plurality of second charge pump circuits. 
     
     
       36. A method according to claim 38 wherein the steps are repeated in succession.