US5798553AExpiredUtility
Trench isolated FET devices, and method for their manufacture
Est. expiryJan 10, 2015(expired)· nominal 20-yr term from priority
H10W 10/0148H10W 10/01H10W 10/17H10W 10/00
56
PatentIndex Score
18
Cited by
33
References
2
Claims
Abstract
A method for improving the subthreshold leakage characteristics of a trench-isolated FET device is described. This method involves first forming a vertical slot within a stack structure disposed on an oxide-covered silicon substrate, and then forming spacers on the sidewalls of the slot. A trench is then etched in the substrate. Removal of the spacers uncovers a horizontal ledge on the exposed surfaces of the oxide-covered substrate, adjacent the trench. The ledge is then perpendicularly implanted with a suitable dopant, thereby suppressing edge conduction in the device. Articles prepared by this method are also described.
Claims
exact text as granted — not AI-modifiedWe claim:
1. A guard structure useful in the preparation of an improved trench-isolated FET device, comprising: a) an oxide-covered substrate which includes a horizontal upper surface; b) at least one isolation trench extending into said substrate; said trench having a trench bottom and substantially vertical trench sidewalls, said sidewalls being substantially perpendicular to said horizontal upper surface of said substrate; c) a horizontal ledge formed by said horizontal upper surface of said oxide-covered substrate, said horizontal ledge being adjacent said trench; and d) a dopant implanted into said horizontal ledge at a concentration of about 5×10 16 to about 5×10 18 dopant atoms per cc, wherein said dopant concentration is about two to four times that of the peak channel doping concentration at the mid-width of said device, wherein said dopant is of the same conductivity type as that of said substrate; and wherein the concentration of said dopant atoms implanted into said sidewalls of said trench is less than about 30% of the concentration of said dopant atoms implanted into said horizontal ledge.
2. A FET device, comprising a guard structure which itself comprises: a) an oxide-covered substrate which includes a horizontal upper surface; b) at least one isolation trench extending into said substrate; said trench having a trench bottom and substantially vertical trench sidewalls, said sidewalls being substantially perpendicular to said horizontal upper surface of said substrate; c) a horizontal ledge formed by said horizontal upper surface of said oxide-covered substrate, said horizontal ledge being adjacent said trench; and d) a implanted into said horizontal ledge at a concentration of about 5×10 16 to about 5×10 18 dopant atoms per cc, wherein said dopant concentration is about two to four times that of the peak channel doping concentration at the mid-width of said device, wherein said dopant is of the same conductivity type as that of said substrate; and wherein the concentration of said second dopant atoms implanted into said sidewalls of said trench is less than about 30% of the concentration of said second dopant atoms implanted into said horizontal ledge.Cited by (0)
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