High-speed predecoding address counter circuit

Abstract

A high-speed predecoding address counter circuit comprising at least three tetrad counters connected in series, each for inputting an external 4-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific logic value at its four output terminals in response to a clock signal, a first clock switching unit responsive to a logical value of a most significant bit of an output signal from a lowest-order one of the at least three tetrad counters, for transferring the clock signal to a higher-order one of at least three tetrad counters, at least one logic unit for detecting whether both most significant bits of output signals from at least two lower-order ones of the at least three tetrad counters have the specific logic value, and at least one second clock switching unit connected between at least one logic unit and at least one of the at least three tetrad counters other than the at least two lower-order tetrad counters, for switching the clock signal to the at least one tetrad counter in response to an output signal from at least one logic unit. According to the present invention, because of a minimized propagation delay time, the address counter circuit generates internal address signals with a high-speed response characteristic with respect to the clock signal.

What is claimed is: 
     
       1. A high-speed predecoding address counter circuit comprising: at least three tetrad counters connected in series, each for inputting an external 4-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific logic value at its four output terminals in response to a clock signal;   first clock switching means responsive to a logical value of a most significant bit of an output signal from a lowest-order one of said at least three tetrad counters, for transferring said clock signal to a higher-order one of said at least three tetrad counters;   at least one logic means for detecting whether both most significant bits of output signals from at least two lower-order ones of said at least three tetrad counters have said specific logic value; and   at least one second clock switching means connected between said at least one logic means and at least one of said at least three tetrad counters other than said at least two lower-order tetrad counters, for switching said clock signal to said at least one tetrad counter in response to an output signal from said at least one logic means.   
     
     
       2. A high-speed predecoding address counter circuit as set forth in claim 1, further comprising third clock switching means for switching said clock signal to said lowest-order tetrad counter in response to a supply voltage being applied thereto. 
     
     
       3. A high-speed predecoding address counter circuit as set forth in claim 1, wherein said at least one logic means is adapted to perform an AND operation. 
     
     
       4. A high-speed predecoding address counter circuit as set forth in claim 1, wherein said first clock switching means are adapted to perform an AND operation. 
     
     
       5. A high-speed predecoding address counter circuit as set forth in claim 1, further comprising a plurality of address switching means each for transferring a decoded address signal from a corresponding one of said at least three tetrad counters to a memory peripheral circuit or decoding an external 2-bit address signal and transferring the decoded address signal to said memory peripheral circuit. 
     
     
       6. A high-speed predecoding address counter circuit comprising: at least three octal counters connected in series, each for inputting an external 8-bit address decoding signal in response to a set signal and cyclically shifting a logic signal with a specific logic value at its eight output terminals in response to a clock signal;   first clock switching means responsive to a logical value of a most significant bit of an output signal from a lowest-order one of said at least three octal counters, for transferring said clock signal to a higher-order one of said at least three octal counters;   at least one logic means for detecting whether both most significant bits of output signals from at least two lower-order ones of said at least three octal counters have said specific logic value; and   at least one second clock switching means connected between said at least one logic means and at least one of said at least three octal counters other than said at least two lower-order octal counters, for switching said clock signal to said at least one octal counter in response to an output signal from said at least one logic means.