Processor having an adaptable mode of interfacing with a peripheral storage device

Abstract

A processor having an adaptable and self-setting mode of interfacing with a peripheral storage device is provided. The processor comprises a variable-parameter controller which enables the processor to adaptably interface with a peripheral storage device. Upon powering up, the controller first interfaces with the peripheral storage device in accordance with a default mode of operation of the peripheral storage device to extract configuration data from the peripheral storage device. The configuration data relates to at least one alternate mode of operation of the peripheral storage device. The controller then interfaces with the peripheral storage device in accordance with the alternate mode of operation. The processor includes a memory device connected to the variable-parameter controller for storing the configuration data so that it is accessible to the controller.

What is claimed is: 
     
       1. A processor having an adaptable mode of interfacing with a peripheral read only memory (ROM) device, wherein said peripheral ROM device is one of a standard-mode ROM device, a nibble-mode ROM device, and a burst-mode ROM device, comprising: a parameter memory for storing information defining timing and control requirements and at least one data access mode of said peripheral ROM device; and   a controller connected to said memory for interfacing with said ROM device in accordance with said stored information.   
     
     
       2. The processor of claim 1, wherein said stored information defines a minimum required first wait time associated with said ROM device. 
     
     
       3. The processor of claim 1, wherein said stored information defines a minimum required burst wait time associated with said ROM device. 
     
     
       4. The processor of claim 1, wherein said stored information defines a data word format associated with said ROM device. 
     
     
       5. The processor of claim 1, further comprising for extracting said information from said ROM device and for storing said information in said parameter memory. 
     
     
       6. The processor of claim 5, wherein said controller interfaces with said ROM device in a default mode of operation to extract said information from said ROM device. 
     
     
       7. The processor of claim 1, further comprising means for extracting said information from a non-volatile memory that is separate from said ROM device and for storing said information in said parameter memory. 
     
     
       8. The processor of claim 7, wherein said non-volatile memory is an EEPROM. 
     
     
       9. A method of interfacing with a peripheral read only memory (ROM) device, wherein said peripheral ROM device is one of a standard-mode ROM device a nibble-mode ROM device, and a burst-mode ROM device, comprising the steps of: communicating with said ROM device in accordance with a default mode of operation of said ROM device;   obtaining configuration data defining timing and control requirements and at least one mode of data access of said ROM device; and   subsequently communicating with said ROM device in accordance with said configuration data.   
     
     
       10. The method of claim 9, wherein the step of obtaining said configuration data is carried out by reading said configuration data from said ROM device while communicating with said ROM device in accordance with said default mode of operation. 
     
     
       11. The method of claim 9, wherein the step of obtaining said configuration data is carried out by reading said configuration data from a non-volatile memory device that is separate from said ROM device. 
     
     
       12. The method of claim 11, wherein the non-volatile memory is an EEPROM. 
     
     
       13. The processor of claim 9, wherein said stored information defines a minimum required first wait time associated with said ROM device. 
     
     
       14. The processor of claim 9, wherein said stored information defines a minimum required burst wait time associated with said ROM device. 
     
     
       15. The processor of claim 9, wherein said stored information defines a data word format associated with said ROM device.