Bit rate doubler for serial data transmission or storage

Abstract

The invention doubles the bit rate for a given media bandwidth as compared to, for example, Manchester encoding. It is applicable to serial transmission or storage of digital data. An arbitrary NRZ data stream is first encoded by a pre-encoding method, such as Manchester, that combines clock and data to represent a single NRZ bit in one clock cycle. A toggle flip flop then re-encodes the pre-encoded waveform, thus generating a double toggle (DT) encoded waveform, which spreads the spectral energy over a larger bandwidth and encodes two NRZ data bits within one transmission clock cycle. In the case of Manchester pre-encoding, data is decoded by determining if there are transitions nearly synchronous with an edge of the recovered clock. For other pre-encoding methods, decoded data is determined by the length of the transition period and the edge polarity of the recovered clock at the leading edge of the transition within the DT encoded waveform. DC offset is reduced by substitution within and inversion of the DT encoded waveform. DC offset compensation of the encoded waveform is either removed prior to data decoding or after a data pre-decoding step; in either case the apparatus searches and detects predetermined substituted patterns in order to correct for the inversion or substitution. Further, a clock state generator is disclosed that uses precision silicon delays in order to generate clock states and quickly synchronize the states to the received encoded waveform. The clock states generate the recovered clocks required to decode data from the encoded waveform.

I claim: 
     
       1. A method of encoding a non-return-to-zero (NRZ) data stream into a serial signal, comprising: (1) initializing a direct current (DC) offset count;   (2) pre-encoding bits of said NRZ data stream to generate a pre-encoded serial signal at a first transmit clock rate having a half bit period that is half the period of said first transmit clock rate, said pre-encoded serial signal representing a single bit of said NRZ data stream within each period of said first transmit clock;   (3) encoding said pre-encoded serial signal to generate said serial signal at a second transmit clock rate that is half of said first transmit clock rate, said serial signal having a limited number of natural transition patterns and representing two bits of said NRZ data stream within each period of said second transmit clock;   (4) comparing the magnitude of said DC offset count to a predetermined count limit range and when said predetermined count limit range is exceeded, then a) searching for and detecting a predetermined replaceable transition pattern within said serial signal, and   b) replacing said predetermined replaceable transition pattern within said serial signal with a predetermined substituted transition pattern that is not one of said limited number of natural transition patterns, said predetermined substituted transition pattern being selected to drive said DC offset count toward the middle of said predetermined count limit range;     (5) updating said DC offset count by adding the number of the half bit periods in which said serial signal has a first value to said DC offset count and subtracting the number of the half bit periods in which said serial signal has the value opposite of said first value from said DC offset count;   (6) repeating steps (2) through (5) for all bits of said NRZ data stream.   
     
     
       2. The method of claim 1 wherein said predetermined replaceable transition patterns have a first value for two of said half bit periods and have a second value that is the opposite of said first value for at least three of said half bit periods and wherein said predetermined substituted transition pattern has said first value for its entire duration. 
     
     
       3. A method of encoding a non-return-to-zero (NRZ) data stream into a serial signal to be transmitted over a local area network, comprising: (1) initializing a direct current (DC) offset count;   (2) pre-encoding bits of said NRZ data stream to generate a pre-encoded serial signal at a first transmit clock rate having a half bit period that is half the period of said first transmit clock rate, said pre-encoded serial signal representing a single bit of said NRZ data stream within each period of said first transmit clock;   (3) encoding said pre-encoded serial signal to generate said serial signal at a second transmit clock rate that is half of said first transmit clock rate, said serial signal having a limited number of natural transition patterns and representing two bits of said NRZ data stream within each period of said second transmit clock;   (4) comparing the magnitude of said DC offset count to a predetermined count limit range and when said predetermined count limit range is exceeded, then a) searching for and detecting a predetermined replaceable transition pattern within said serial signal, and   b) replacing said predetermined replaceable transition pattern within said serial signal with a predetermined substituted transition pattern that is not one of said limited number of natural transition patterns, said predetermined substituted transition pattern being selected to drive said DC offset count toward the middle of said predetermined count limit range;     (5) updating said DC offset count by adding the number of the half bit periods in which said serial signal has a first value to said DC offset count and subtracting the number of the half bit periods in which said serial signal has the value opposite of said first value from said DC offset count;   (6) outputting said serial signal for transmission over a local area network;   (7) repeating steps (2) through (6) for all bits of said NRZ data stream.   
     
     
       4. The method of claim 3 wherein said replaceable transition patterns have a first value for two of said half bit periods and a second value that is the opposite of said first value for at least three of said half bit periods and wherein said substituted transition pattern has said first value for its entire duration. 
     
     
       5. The method of any of claims 1 to 4 wherein said pre-encoding step uses Manchester encoding. 
     
     
       6. The method of any of claims 1 to 4 wherein said pre-encoding step uses Biphase-Level encoding. 
     
     
       7. The method of any of claims 1 to 4 wherein said pre-encoding step uses Biphase-Mark (FM1) encoding. 
     
     
       8. The method of any of claims 1 to 4 wherein said pre-encoding step uses Biphase-Space (FM0) encoding. 
     
     
       9. The method of any of claims 1 to 4 wherein said pre-encoding step uses Differential-Biphase-Level encoding. 
     
     
       10. The method of any of claims 1 to 4 wherein said pre-encoding step uses Differential-Manchester encoding. 
     
     
       11. An apparatus for decoding a non-return-to-zero (NRZ) data stream from a serial signal, comprising: clock recovery means, responsive to said serial signal, to generate a recovered clock, said recovered clock having a period one half bit in duration indicating the timing of transitions within said serial signal;   pre-decoder means to generate a preliminary decoded data stream responsive to said serial signal and to said recovered clock;   offset replacement decoder means coupled to said clock recovery means and said pre-decoder means, responsive to said preliminary decoded data stream, said serial signal, and said recovered clock, to generate said NRZ data stream from said preliminary decoded data stream by detecting predetermined substituted transition patterns within said serial signal by detecting a predetermined sequential number of half bit periods with no transition and, when detected, correcting said preliminary decoded data stream to produce said NRZ data stream.   
     
     
       12. An apparatus in accordance with claim 11, wherein said offset replacement decoder means further detects predetermined substituted transition patterns within said serial signal having at least five of said half bit periods of the same value and corrects said preliminary decoded data stream by changing the value of a single bit to generate said NRZ data stream. 
     
     
       13. An apparatus for decoding a non-return-to-zero (NRZ) data stream from a serial signal received from a local area network, comprising: clock recovery means, responsive to said serial signal received from said local area network, to generate a recovered clock, said recovered clock having a period one half bit in duration indicating the timing of transitions within said serial signal;   pre-decoder means to generate a preliminary decoded data stream responsive to said serial signal received from said local area network and to said recovered clock;   offset replacement decoder means coupled to said clock recovery means and said pre-decoder means, responsive to said preliminary decoded data stream, said serial signal, and said recovered clock, to generate said NRZ data stream from said preliminary decoded data stream by detecting predetermined substituted transition patterns within said serial signal by detecting a predetermined sequential number of half bit periods with no transition and, when detected, correcting said preliminary decoded data stream to produce said NRZ data stream.   
     
     
       14. An apparatus in accordance with claim 13, wherein said offset replacement decoder means further detects predetermined substituted transition patterns within said serial signal having at least five of said half bit periods of the same value and corrects said preliminary decoded data stream by changing the value of a single bit to generate said NRZ data stream. 
     
     
       15. The apparatus of any of claims 11 to 14 wherein, in the case where a transition of said serial signal synchronizes with said recovered clock, said pre-decoder means generates a one within said preliminary decoded data stream, and   in the case where no transition of said serial signal synchronizes with said recovered clock, said pre-decoder means generates a zero within said preliminary decoded data stream,   whereby said pre-decoder means decodes said serial signals encoded by a Manchester pre-encoding means.   
     
     
       16. The apparatus of any of claims 11 to 14 wherein, in the case where a transition of said serial signal synchronizes with said recovered clock, said pre-decoder generates a zero within said preliminary decoded data stream, and   in the case where no transition of said serial signal synchronizes with said recovered clock, said pre-decoder generates a one within said preliminary decoded data stream,   whereby said pre-decoder means decodes said serial signals encoded by a Biphase-Level pre-encoding means.   
     
     
       17. An apparatus for decoding a non-return-to-zero (NRZ) data stream from a serial signal, comprising: clock recovery means, responsive to said serial signal, to generate a recovered clock, said recovered clock having a period one half bit in duration indicating the timing of transitions within said serial signal;   offset replacement decoder means, responsive to said serial signal and to said recovered clock, to generate a corrected encoded data stream by detecting predetermined substituted transition patterns within said serial signal by detecting a predetermined sequential number of half bit periods with no transition and when detected, correcting said serial signal prior to its being output as said corrected encoded data stream;   data decoder means to generate said NRZ data stream responsive to said corrected encoded data stream and to said recovered clock.   
     
     
       18. An apparatus in accordance with claim 17, wherein said offset replacement decoder means detects said predetermined substituted transition patterns within said serial signal having a sequence of at least five of said half bit periods all of the same value, corrects said serial signal into said corrected encoded data stream by inverting said serial signal after the first two half bit periods within said sequence of half bit periods. 
     
     
       19. An apparatus for decoding a non-return-to-zero (NRZ) data stream from a serial signal received from a local area network, comprising: clock recovery means, responsive to said serial signal, to generate a recovered clock, said recovered clock having a period one half bit in duration indicating the timing of transitions within said serial signal;   offset replacement decoder means, responsive to said serial signal and to said recovered clock, to generate a corrected encoded data stream by detecting predetermined substituted transition patterns within said serial signal by detecting a predetermined sequential number of half bit periods with no transition and when detected, correcting said serial signal prior to its being output as said corrected encoded data stream;   data decoder means to generate said NRZ data stream responsive to said corrected encoded data stream and to said recovered clock.   
     
     
       20. An apparatus in accordance with claim 19, wherein said offset replacement decoder means detects said predetermined substituted transition patterns within said serial signal having a sequence of at least five of said half bit periods all of the same value, corrects said serial signal into said corrected encoded data stream by inverting said serial signal after the first two half bit periods within said sequence of half bit periods. 
     
     
       21. The apparatus of any of claims 17 to 20 wherein in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the rising edge of said recovered clock, when said transition pattern is four half bit periods all having the same value, then said data decoder means generates two zero bits within said NRZ data stream, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream,   when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a zero bit followed by a one bit within said NRZ data stream;   in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the falling edge of said recovered clock, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream,   whereby said data decoder means decodes said serial signals encoded by a Biphase-Mark (FM1) pre-encoding means.   
     
     
       22. The apparatus of any of claims 17 to 20 wherein in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the rising edge of said recovered clock, when said transition pattern is four half bit periods all having the same value, then said data decoder means generates two zero bits within said NRZ data stream, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a zero bit followed by a one bit within said NRZ data stream;   in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the falling edge of said recovered clock, when said transition pattern is two half bit periods all having the same value, then said data decoder means decodes it into a single one bit within said NRZ data stream,   when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream,   whereby said data decoder means decodes said serial signals encoded by a Differential-Manchester pre-encoding means.   
     
     
       23. The apparatus of any of claims 17 to 20 wherein in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the rising edge of said recovered clock, when said transition pattern is four half bit periods all having the same value, then said data decoder means generates two one bits within said NRZ data stream, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a one bit followed by a zero bit within said NRZ data stream;   in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the falling edge of said recovered clock, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream,   whereby said data decoder means decodes said serial signals encoded by a Biphase-Space (FM0) pre-encoding means.   
     
     
       24. The apparatus of any of claims 17 to 20 wherein in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the rising edge of said recovered clock, when said transition pattern is four half bit periods all having the same value, then said data decoder means generates two one bits within said NRZ data stream, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a one bit followed by a zero bit within said NRZ data stream;   in the case where the leading edge of a transition pattern within said corrected encoded data stream aligns with the falling edge of said recovered clock, when said transition pattern is two half bit periods all having the same value, then said data decoder means generates a single zero bit within said NRZ data stream, when said transition pattern is three half bit periods all having the same value, then said data decoder means generates a single one bit within said NRZ data stream,   whereby said data decoder means decodes said serial signals encoded by a Differential-Biphase-Level pre-encoding means.