Transistor overload protection assembly and method with time-varying power source

Abstract

An overload protection assembly and method for overload protection of a transistor includes a switching transistor connected between a load at a first terminal and a power source at a second terminal. A measuring circuit measures the voltage levels at the first and second terminals. The first terminal is measured before and after the measurement of the second terminal, and averaged to produce its voltage level. The measured voltage levels from the first and second terminals are subtracted from one another and the difference compared to preset limits to determine overload conditions. If overload conditions exist, the measuring circuit turns off the transistor.

What is claimed is: 
     
       1. An overload protection assembly comprising: a switching transistor connected between a load at a first transistor terminal and a power source at a second transistor terminal, and having a control terminal controlling said transistor to on and off states; and   a measuring circuit connected to and controlling said control terminal of said switching transistor for independently measuring a first voltage level at said first transistor terminal and a second voltage level at said second transistor terminal and for controlling said switching transistor to the off state when said first voltage level has a predetermined relationship to said second voltage level, said measuring circuit including a calculator for subtracting said first voltage level from said second voltage level for producing a voltage drop signal;   said measuring circuit includes a comparator for comparing said voltage drop signal to a plurality of set limits to control said transistor to the off state when there is a predetermined relationship to said set limits, said set limits including a first set limit allowing continued operation of said switching transistor, a third set limit immediately controlling said transistor to said off state, and a second set limit which accumulate the voltage drop signals overtime and compare to an accumulated limit to control said transistor to the off state upon determining a predetermined relationship to the accumulated limit.   
     
     
       2. An overload protection assembly as set forth in claim 1 wherein said switching transistor includes a MOSFET having a gate as said control terminal, a drain as said first terminal and a source as said second terminal. 
     
     
       3. An overload protection assembly as set forth in claim 1 wherein said measuring circuit includes an analog-to-digital converter for converting said first and second voltage levels to a digital signal to said calculator. 
     
     
       4. An overload protection assembly as set forth in claim 3 wherein said measuring circuit comprises a microprocessor. 
     
     
       5. An overload protection assembly as set forth in claim 2 wherein said switching transistor includes a driving transistor connected between said measuring circuit and said MOSFET. 
     
     
       6. An overload protection assembly comprising: a switching transistor connected between a load at a first transistor terminal and a power source at a second transistor terminal, and having a control terminal controlling said switching transistor into on and off states;   a measuring circuit connected to and controlling said control terminal of said switching transistor for independently measuring a first voltage level at said first transistor terminal and a second voltage level at said second transistor terminal and for controlling said switching transistor to the off state when said first voltage level has a predetermined relationship to said second voltage level; and   said measuring circuit including a calculator circuit for measuring a first initial voltage level at said first transistor terminal at a first time prior to measuring said second voltage level at a second time greater than said first time, and measuring a second initial voltage level at said first transistor terminal at a third time after measuring said second voltage level, and averaging the first and second initial voltage levels to produce said first voltage level.   
     
     
       7. A method of overload protecting a switching transistor comprising the steps of: sensing a first voltage level at a first transistor terminal of a transistor which is connected to power;   independently sensing a second voltage level at a second transistor terminal of the transistor which is connected to a load;   sensing a first initial voltage level at the first transistor terminal prior to sensing the second voltage level, and sensing a second initial voltage level at the first transistor terminal after sensing the second voltage level;   averaging the first and second initial voltage levels to obtain the first voltage level;   comparing the first and second voltage levels to at least one set limit; and   controlling the transistor to an on or off state when the first and second voltage levels have a predetermined relationship to the set limits.   
     
     
       8. A method as set forth in claim 7 further including sensing the first and second initial voltage levels and the second voltage level at equal time intervals. 
     
     
       9. A method as set forth in claim 7 including subtracting the averaged first voltage level from the second voltage level to obtain a voltage drop signal. 
     
     
       10. A method as set forth in claim 9 including comparing the voltage drop signal to a plurality of set limits to control the transistor. 
     
     
       11. A method as set forth in claim 7 including the transistor comprising a MOSFET having a drain as the first transistor terminal and a source as the second is transistor terminal. 
     
     
       12. A method as set forth in claim 7 including the transistor comprising a bipolar transistor having a collector as the first transistor terminal and a emmitter as the second transistor terminal. 
     
     
       13. A method as set forth in claim 10 including allowing said transistor to remain in said on state when said voltage drop signal is within a first set of limits. 
     
     
       14. A method as set forth in claim 13 including switching said transistor to said off state when said voltage drop signal is within a second set of limits and an accumulated amount of voltage drop signals within a time has a predetermined relationship to an accumulated limit. 
     
     
       15. A method as set forth in claim 14 including immediately switching said transistor to said off state when said voltage drop signal is within a third set of limits.