Three state output method and apparatus for high speed amplifiers

Abstract

Three state high speed amplifiers having a high output impedance when disabled and a minimum glitch when enabled and disabled. The amplifiers utilize complementary emitter followers for the output stage. When the amplifiers are disabled, circuitry provided for the purpose drives is responsive to the voltage on the output of the amplifier to maintain the base-emitter voltages of the output emitter followers at a substantially constant level below the turn-on voltages of the transistors, such as substantially zero volts. When the amplifier is enabled, the circuitry is also responsive to the voltage on the output of the amplifier, but this time to allow the base-emitter voltages of the output emitter followers to at least freely rise to the turn-on voltages of the transistors. Thus the reverse base-emitter voltage of the output transistors when the circuit is disabled is limited, and the output glitch on enable and disable is minimal because of the limited base-emitter voltage swing of the output transistors between disable and enable.

I claim: 
     
       1. A high speed amplifier having a low output impedance when enabled and a high output impedance when disabled comprising: first and second complimentary transistors each having an emitter, a base and a collector, the first and second complimentary transistors having their emitters coupled together and to an amplifier output, and their collectors coupled to first and second power supply terminals respectively;   a first circuit coupled to the bases of the first and second transistors controllably providing currents to control the output responsive to an amplifier input;   a second circuit coupled to the bases of the first and second transistors and to the amplifier output, the second circuit providing controlled base-emitter voltages, independent of the amplifier output, to the first and second transistors to hold the first and second transistors off when the amplifier is disabled, and not effecting the base-emitter voltages of the first and second transistors when the amplifier is enabled.   
     
     
       2. The high speed amplifier of claim 1 wherein the second circuit provides approximately zero base-emitter voltages to the first and second transistors to hold the first and second transistors off when the amplifier is disabled. 
     
     
       3. The high speed amplifier of claim 2 wherein the approximately zero base-emitter voltages provided to the first and second transistors to hold the first and second transistors off when the amplifier is disabled are voltages equal to the amplifier output plus the difference in the base-emitter voltages of two additional transistors, each having an emitter, a base and a collector. 
     
     
       4. The high speed amplifier of claim 1 wherein the first circuit comprises third and fourth complimentary transistors each having an emitter, a base and a collector, the bases of the third and fourth transistors being coupled to an amplifier input, the emitters of each of the third and fourth transistors being coupled to a current source and to the base of the complementary one of the first and second transistors, and the collectors of the third and fourth transistors being coupled to first and second power supply terminals. 
     
     
       5. The high speed amplifier of claim 1 wherein the second circuit includes first and second nodes, the second circuit causing the voltage of the first and second nodes to track the amplifier output within a magnitude of one VBE when the amplifier is enabled and to track the amplifier output within a magnitude of one VBE when the amplifier is disabled. 
     
     
       6. The high speed amplifier of claim 5 wherein the second circuit changes the voltage of each of the first and second nodes by 2 VBE between when the amplifier is enabled and when it is disabled. 
     
     
       7. A method of operating a high speed amplifier to provide a low output impedance when enabled and a high output impedance when disabled: the amplifier having; first and second complimentary transistors each having an emitter, a base and a collector, the first and second complimentary transistors having their emitters coupled together and to an amplifier output, and their collectors coupled to first and second power supply terminals respectively;   a first circuit coupled to the bases of the first and second transistors controllably providing currents to control the output responsive to an amplifier input;     the method comprising the steps of;   a) holding the base-emitter voltages of the first and second transistors to values substantially independent of the amplifier output to hold the first and second transistors off when the amplifier is disabled; and,   b) not effecting the base-emitter voltages of the first and second transistors when the amplifier is enabled.   
     
     
       8. The method of claim 7 wherein in step a), the base-emitter voltages of the first and second transistors are held to substantially zero volts. 
     
     
       9. The method of claim 8 wherein in step a) the approximately zero base-emitter voltages of the first and second transistors are voltages equal to the amplifier output plus the difference in the base-emitter voltages of two additional transistors, each having an emitter, a base and a collector. 
     
     
       10. The method of claim 7 wherein the second circuit includes first and second nodes, the voltage of the first and second nodes tracking the amplifier output within one VBE when the amplifier is enabled and tracking the amplifier output within one VBE when the amplifier is disabled. 
     
     
       11. The method of claim 10 wherein the voltage of each of the first and second nodes changes by 2 VBE between when the amplifier is enabled and when it is disabled. 
     
     
       12. In a high speed amplifier having a low output impedance when enabled and a high output impedance when disabled, a circuit coupled to an output transistor having an emitter coupled to an amplifier output, a collector coupled to a first power supply terminal, and a base coupled to an input circuit which controllably provides current to control the output responsive to an amplifier input, the circuit comprising: a first transistor of a first conductivity type having an emitter, a base coupled to the amplifier output, and a collector coupled to the first power supply terminal;   a second transistor of a second conductivity type having an emitter coupled to the base of the output transistor, a base coupled to a switched current source and the emitter of the first transistor, and a collector coupled to a second power supply terminal;   wherein the first and second transistors hold the output transistor off by providing a zero base-emitter voltage, independent of the amplifier output, when the amplifier is disabled, and not effecting the base-emitter voltage of the output transistor when the amplifier is enabled.   
     
     
       13. The circuit of claim 12 wherein the switched current source comprises: a control signal; and   a third transistor of the first conductivity type, having an emitter coupled to the second power supply terminal through a current source, a collector coupled to the base of the second transistor, and a base coupled to the control signal, the control signal enabling the third transistor when the amplifier is disabled and disabling the third transistor when the amplifier is enabled.   
     
     
       14. The circuit of claim 12 wherein the approximately zero base-emitter voltage provided to the output transistor to hold the output transistor off when the amplifier is disabled is a voltage equal to the amplifier output plus the difference in the base-emitter voltages of the first and second transistors. 
     
     
       15. The circuit of claim 12 wherein the first circuit comprises a fourth transistor of the second conductivity type having an emitter coupled to the first power supply terminal through a second current source and to the emitter of the second transistor, a base coupled to the amplifier input, and a collector coupled to the second power supply terminal. 
     
     
       16. The circuit of claim 12 further comprising a node, wherein the voltage of the node tracks the amplifier output within a magnitude of one VBE when the amplifier is enabled and tracks the amplifier output within a magnitude of one VBE when the amplifier is disabled. 
     
     
       17. The circuit of claim 16 wherein the node voltage changes by 2 VBE between when the amplifier is enabled and when it is disabled.