Method and apparatus utilizing a region based page table walk bit

Abstract

A method and an apparatus for translating a virtual address into a physical address in a multiple region virtual memory environment. In one embodiment, a translation lookaside buffer (TLB) is configured to provide page table entries to build a physical address. The TLB is supplemented with a virtual hash page table (VHPT) to provide TLB entries in the occurrences of TLB misses. An alternate software replacement scheme may be utilized on a per region basis instead of the default page table walk of the VHPT with a dedicated bit associated with each particular region of the disclosed virtual address space. A VHPT walk is performed only if the particular bit for the particular region and a master enable bit are both enabled. Otherwise, the alternate software replacement routine is performed to provide TLB replacements in the occurrences of TLB misses.

What is claimed is: 
     
       1. In a computer system having a processor and a memory coupled to the processor, an address translation mechanism configured to translate a virtual address into a physical address, the virtual address addressing a virtual memory organized into regions, comprising: a region register having an enable indicator, the region register corresponding with a region of the virtual address;   a translation lookaside buffer (TLB) coupled to the region register and coupled to receive the virtual address, the TLB configured to contain a page entry used to determine the physical address;   a default replacing mechanism configured to provide the TLB with the page entry in response to a TLB miss and a first state of the region register enable indicator; and,   an alternate replacement mechanism configured to provide to the TLB the page entry to determine the physical address in response to the TLB miss and a second state of the region register enable indicator.   
     
     
       2. The address translation mechanism described in claim 1 further comprising a master enable indicator, the default replacing mechanism configured to provide to the TLB with the page entry in response to the TLB miss, the first state of the region register enable indicator and a first state of the master enable indicator, the alternate replacement mechanism configured to provide to the TLB the page entry to determine the physical address in response to the TLB miss and a second state of the master enable indicator. 
     
     
       3. The address translation mechanism described in claim 2 wherein the default replacing mechanism comprises a virtual hash page table (VHPT) stored in the memory and a VHPT searching mechanism, the VHPT searching mechanism configured to search the VHPT for the TLB page entry in response to the TLB miss, the first state of the region register enable indicator and the first state of the master enable indicator. 
     
     
       4. The address translation mechanism described in claim 1 wherein the alternate replacement mechanism comprises an alternate TLB vector stored in the memory, the alternate TLB vector pointing to an alternate TLB routine stored in the memory, the alternate TLB routine when executed by the processor configured to provide the page entry to determine the physical address. 
     
     
       5. The address translation mechanism described in claim 4 wherein the alternate TLB routine comprises a performance monitoring routine. 
     
     
       6. The address translation mechanism described in claim 4 wherein the alternate TLB vector comprises an alternate instruction TLB vector and an alternate data TLB vector, the alternate instruction TLB vector pointing to an alternate instruction TLB routine stored in the memory, the alternate data TLB vector pointing to an alternate data TLB routine stored in the memory. 
     
     
       7. In a computer system having a processor and a memory coupled to the processor, a method for translating a virtual address into a physical address, the virtual address addressing a virtual memory organized into regions, the method comprising the steps of: searching a translation lookaside buffer (TLB) for a page entry corresponding with the virtual address;   searching a page table stored in the memory for the page entry if there is a TLB miss in the step of searching the TLB and if a region register enable indicator is in a first state, the region register enable indicator corresponding with a region of the virtual address;   performing an alternate TLB replacement routine for the page entry if there is the TLB miss in the step of searching the TLB and if the region register enable indicator is in a second state; and, determining the physical address.   
     
     
       8. The method described in claim 7 wherein the step of searching the page table is performed when the region register enable indicator is in the first state and a master enable indicator is in a first state. 
     
     
       9. The method described in claim 7 wherein the step of performing the alternate TLB replacement routine is performed when a master enable indicator is in a second state. 
     
     
       10. The method described in claim 7 wherein the step of performing the alternate TLB replacement routine includes the step of accessing an alternate TLB miss vector to determine an address of the alternate TLB replacement routine. 
     
     
       11. The method described in claim 7 wherein the step of performing the alternate TLB replacement routine includes the step of accessing an alternate instruction TLB miss vector to determine an address of the alternate instruction TLB replacement routine. 
     
     
       12. The method described in claim 7 wherein the step of performing the alternate TLB replacement routine includes the step of accessing an alternate data TLB miss vector to determine an address of the alternate data TLB replacement routine. 
     
     
       13. The method described in claim 7 wherein the step of performing the alternate TLB replacement routine includes the step of performing a performance monitoring routine.