Apparatus, system and method for identifying semiconductor memory access modes

Abstract

An apparatus, system and method for identifying an access mode of a semiconductor memory in a data processing system, characterized by significant reduction of the possibility of erroneous identification of the access mode. A semiconductor memory has an access circuit bank with plurality of selectable circuits only one of which is activated, each selectable circuit respectively associated with a selectable semiconductor memory access mode, the access mode selection typically being accomplished by selectively blowing fuses associated with the corresponding selectable circuits. A semiconductor memory access mode is correctly identified by associating, in response to a test signal for determining the fuse status, the respective activated selectable circuit with its corresponding access mode.

What is claimed is: 
     
       1. A memory comprising: a plurality of memory cells in an array having at least two coordinates;   access circuitry connected to any of said plurality of memory cells according to a designated value of at least one of said at least two coordinates, said access circuitry including a plurality of selectable circuits respectively associated with a plurality of different access modes and selecting circuitry for selecting one of said selectable circuits to connect to any of said plurality of memory cells in an associated one of said plurality of different access modes; and   test signal circuitry having an input terminal for a test signal for identifying in response to a test signal said selected one of said selectable circuits, said test signal circuitry including a plurality of connections each connection to a respective one of said plurality of selectable circuits, and output circuitry for indicating said selected one of said selectable circuits.   
     
     
       2. The memory according to claim 1, wherein: each of said plurality of selectable circuits includes a node operable between a first and second voltage values;   said selecting circuitry comprises a circuit driving said node from one to the other of said first and second voltage values; and   each of said plurality of connections of said test signal circuitry connects to a respective one of said plurality of selectable circuits at a respective said node.   
     
     
       3. The memory according to claim 2, further including a plurality of multiplexers, and wherein: said input terminal for a test signal is connected to said respective node through a respective one of said plurality of multiplexers.   
     
     
       4. The memory according to claim 3, wherein: said output circuits comprises an output terminal and a buffer circuit for connecting said plurality of multiplexers to said output terminal.   
     
     
       5. The memory according to claim 4, wherein: said output circuitry further comprises a plurality of inverter circuits, each responsive to a respective one of said multiplexers and connected to said output terminal.   
     
     
       6. The memory according to claim 1, wherein: the plurality of selectable circuits include: a first selectable circuit for a fast page access mode; and   a second selectable circuit for a mode different from said fast page access mode; and     each of said plurality of selectable circuits includes a node operable between a first and second voltage values;   said selecting circuitry comprises a driving circuit that drives said node of said first circuit from one to the other of said first and second voltage values without driving said node of said second circuit between said first and second voltage values; and   each of said plurality of connections of said test signal circuitry connects to said respective one of said plurality of selectable circuits at a respective said node.   
     
     
       7. The memory according to claim 1, wherein: the plurality of selectable circuits include: a first selectable circuit for an extended data-out access mode; and   a second selectable circuit for a mode different from said extended data-out access mode; and   each of said plurality of selectable circuits includes a node operable between a first and second voltage values;   said selecting circuitry comprises a circuit that drives said node of said first selectable circuit from one to the other of said first and second voltage values without driving said node of said second selectable circuit between said first and second voltage values; and   each of said plurality of connections of said test signal circuitry connects to said respective one of said plurality of selectable circuits at a respective said node.   
     
     
       8. The memory according to claim 1, wherein: the plurality of selectable circuits include: a first selectable circuit for a burst extended data-out access mode; and   a second selectable circuit for a mode different from said burst extended data-out access mode; and   each of said plurality of selectable circuits includes a node operable between a first and second voltage values;   said selecting circuitry comprises a circuit that drives said node of said first circuit from one to the other of said first and second voltage values without driving said node of said second circuit between said first and second voltage values; and   each of said plurality of connections of said test signal circuitry connects to said respective one of said plurality of selectable circuits at a respective said node.   
     
     
       9. A data processing system including input and output terminals and a processor connected between said input and output terminals, said processor comprising at least one central processing unit and a memory, said memory comprising: a plurality of memory cells in an array having at least two coordinates;   access circuitry connecting to any of said plurality of memory cells according to a designated value of at least one of said at least two coordinates, said access circuitry including a plurality of selectable circuits respectively associated with a plurality of different access modes and selecting circuitry for selecting one of said selectable circuits to connect to any of said plurality of memory cells in an associated one of said plurality of different access modes; and   test signal circuitry having an input terminal for a test signal for identifying in response to said test signal a selected one of said selectable circuits or said associated one of said plurality of different modes, said test signal circuitry including a plurality of connections, each to a respective one of said plurality of selectable circuits, and an output circuitry indicating said selected one of said selectable circuits.   
     
     
       10. The data processing system according to claim 9, wherein: each of said plurality of selectable circuits includes a node operable between a first and second voltage values;   said selecting circuitry comprises a circuit that drives said node from one to the other of said first and second voltage values; and   each of said plurality of connections of said test signal circuitry connects to said respective one of said plurality of selectable circuits at a respective said node.   
     
     
       11. The data processing system according to claim 10, further including a plurality of multiplexers, and wherein: said input terminal for a test signal is connected to said respective node through a respective one of said plurality of multiplexers.   
     
     
       12. The data processing system according to claim 11, wherein: said output circuitry comprises an output terminal and a buffer circuit for connecting said plurality of multiplexers to said output terminal.   
     
     
       13. The data processing system according to claim 12, wherein: said output circuitry further comprises a plurality of logic circuits, each responsive to a respective one of said multiplexers and connected to said output terminal.   
     
     
       14. The data processing system according to claim 9, wherein: the plurality of selectable circuits include: a first circuit for a fast page access mode; and   a second circuit for a mode different from said fast page access mode; and     each of said plurality of selectable circuits includes a node operable between a first and second voltage values;   said selecting circuit comprises a circuit that drives said node of said first circuit from one to the other of said first and second voltage values without driving said node of said second circuit between said first and second voltage values; and   each of said plurality of connections of said test signal circuitry connects to said respective one of said plurality of selectable circuits at a respective said node.   
     
     
       15. The data processing system according to claim 9, wherein: the plurality of selectable circuits include: a first circuit for an extended data-out access mode; and   a second circuit for a mode different from said extended data-out access mode; and     each of said plurality of selectable circuits includes a node operable between a first and second voltage values;   said selecting circuit comprises a circuit that drives said node of said first circuit from one to the other of said first and second voltage values without driving said node of said second circuit between said first and second voltage values; and   each of said plurality of connections of said test signal circuitry connects to said respective one of said plurality of selectable circuits at a respective said node.   
     
     
       16. The data processing system according to claim 9, wherein: the plurality of selectable circuits include: a first circuit for a burst extended data-out access mode; and   a second circuit for a mode different from said burst extended data-out access mode; and     each of said plurality of selectable circuits includes a node operable between a first and second voltage values;   said selecting circuitry comprises a circuit that drives said node of said first circuit from one to the other of said first and second voltage values without driving said node of said second circuit between said first and second voltage values; and   each of said plurality of connections of said output circuitry connects to said respective one of said plurality of selectable circuits at a respective said node.   
     
     
       17. A method of identifying a memory comprising the steps of: selecting one of a plurality of selectable access modes for said memory each associated with one of a plurality of access mode control circuits each coupled to a node, by establishing an activating signal at said coupled node;   applying a test signal to said memory via one of said plurality of access mode control circuits;   providing input/output signals with said activating signal to produce a third signal indicative of selection or nonselection of a respective access mode in response to said test signal; and   applying said third signal to a respective output terminal for each of said plurality of access mode circuits as a respective output signal, whereby said selected access mode is identified by one output signal that differs among the output signals of each of said plurality of access mode circuits.   
     
     
       18. The method according to claim 17, wherein: the selecting step includes the step of selecting one among the plurality of differing access mode circuits that respectively provide different speeds of sending data from the memory.   
     
     
       19. The method according to claim 18, wherein: the test signal applying step applies the test signal to a plurality of different sites in the memory, each of said sites being associated with a respective one of said plurality of differing access mode circuits.   
     
     
       20. The method according to claim 19, wherein: the third signal applying step includes the step of buffering the multiplexed signals from the respective output terminal.   
     
     
       21. The method according to claim 20, wherein: the test signal applying step includes the step of separately processing the result of multiplexing the multiplexed signals in each of said plurality of differing access mode circuits.   
     
     
       22. The method according to claim 21, wherein the processing step includes the step of providing the test signal, the third signal, and input/output data signals for the memory to respective first, second, and third input terminals of each of a first and second multiplexer circuits. 
     
     
       23. The method according to claim 22, including the step of providing a first circuit for a fast page access mode as said selected one of said plurality of differing access mode circuits. 
     
     
       24. The method according to claim 22, including the step of providing a first circuit for an extended data-out access mode as said selected one of said plurality of differing access mode circuits. 
     
     
       25. The method according to claim 22, including the step of providing a first circuit for a burst extended data-out access mode as said selected one of said plurality of differing access mode circuits. 
     
     
       26. The method according to claim 22, wherein the step of providing the input/output data signals includes the step of providing respective signals bearing data to be stored in, or data read out from, said memory. 
     
     
       27. The memory according to claim 1, wherein the selecting circuitry includes a blown fuse. 
     
     
       28. The data processing systems according to claim 9, wherein the selecting circuitry includes a blown fuse. 
     
     
       29. The method according to claim 17, wherein the selecting step includes the step of blowing a fuse.