Electron emitting semiconductor device

Abstract

An electron emitting semiconductor device is provided with a P-type semiconductor layer arranged on a semiconductor substrate having an impurity concentration. A Schottky barrier electrode is arranged on a surface of the P-type semiconductor layer. Plural P + -type area units are positioned under and facing the Schottky barrier electrode. An N + -type area is disposed in the vicinity of the P + -type units. The impurity concentration is such as to cause an avalanche breakdown in at least a portion of the surfaces.

What is claimed is: 
     
       1. An electron emitting semiconductor device comprising: a P-type semiconductor layer formed on a semiconductor substrate;   a Schottky barrier electrode formed on said P-type semiconductor layer;   a plurality of point-shaped P +  area units positioned under and facing said Schottky barrier electrode; and   an N +  type area in the vicinity of said P +  area units, wherein said P+ area units limit points of electron emission.     
     
     
       2. An electron emitting semiconductor device according to claim 1, wherein said Schottky barrier electrode comprises at least a material selected from the group consisting of Gd, LaB 6 , TiC, ZrC, HfC, SmB 6 , GdB 6 , WSi 2 , TiSi 2 , ZrSi 2  and GdSi 2 . 
     
     
       3. An electron emitting semiconductor device according to claim 1, wherein said P-type semiconductor layer comprises at least a material selected from the group consisting of Si, Ge, GaAs, GaP, AlAs, GaAsP, AlGaAs, SiC and BP. 
     
     
       4. An electron emitting semiconductor device according to claim 1, wherein said Schottky barrier electrode has a thickness of at most 20 nm. 
     
     
       5. An electron emitting semiconductor device according to claim 4, wherein said Schottky barrier electrode has a thickness in a range from 5 nm to 15 nm. 
     
     
       6. An electron emitting semiconductor device according to claim 1, wherein said plurality of P +  -type area units are shaped into predetermined configurations. 
     
     
       7. A device according to claim 1, wherein said N +  type area is disposed so as to surround said P +  area units and is annular.