Non-volatile digital circuits using ferroelectric capacitors

Abstract

A circuit including a ferroelectric capacitor can be used to store the value of nodes of volatile logic elements in a logic circuit. In this manner, the state of a complex logic circuit, such as a CPU or an I/O device, can be stored in the non-volatile ferroelectric capacitors. After an accidental or planned power outage, the non-volatile ferroelectric capacitors can be used to restore the values of the nodes. Additionally, a planned power loss can be save system power in circuits that are power consumption sensitive.

What is claimed is: 
     
       1. An apparatus including: a logic circuit including a volatile logic element having a node defining a logic state at a first time, the node of logic element being connected to an input of another volatile logic element of the logic circuit; and   circuitry operatively connected to the volatile logic element, the circuitry including a ferroelectric capacitor, the ferroelectric capacitor defining a voltage versus charge hysteresis curve, the circuitry adapted to set the position of the ferroelectric capacitor on the hysteresis curve depending on a value of the logic state at the node, wherein the value at the node is lost when the power to the apparatus is off and the circuitry is further adapted to restore the value of the logic state at the node of the volatile logic element using the ferroelectric capacitor when power is restored to the apparatus.   
     
     
       2. The apparatus of claim 1, wherein the volatile logic element is a latch. 
     
     
       3. The apparatus of claim 1, wherein the volatile logic element is a flip-flop. 
     
     
       4. The apparatus of claim 1, wherein the volatile logic element includes matched pair of inverters. 
     
     
       5. The apparatus of claim 1, wherein the logic circuit comprises a central processing unit. 
     
     
       6. The apparatus of claim 1, wherein an additional volatile logic element having nodes associated with an additional circuitry includes ferroelectric capacitors to store and restore the value of the node. 
     
     
       7. The apparatus of claim 6, wherein same control lines are sent to the circuitry and the additional circuitry. 
     
     
       8. The apparatus of claim 1, further comprising a controller for sending control signals to the circuitry. 
     
     
       9. The apparatus of claim 1, wherein the circuitry is operably connected to an additional node of the volatile logic element, the additional node normally having the obverse value from said node, the circuitry having an additional ferroelectric capacitor to store the value of the additional node.   
     
     
       10. The apparatus of claim 1, wherein the circuitry comprises a pre-charge circuit to pull the value at node toward ground. 
     
     
       11. The apparatus of claim 1, wherein the circuitry comprises an isolating transistor that allows the ferroelectric capacitor to be isolated from the node. 
     
     
       12. The apparatus of claim 11, wherein the circuitry comprises a pre-charge circuitry positioned with respect to the isolating transistor so that the voltage on one side of the ferroelectric capacitor can be pulled down while isolating transistor isolates the node of the volatile logic element. 
     
     
       13. An apparatus including: a logic circuit including a volatile logic element having a node defining a logic state at a first time, the node of logic element being connected to an input of another volatile logic element of the logic circuit; and   circuitry operatively connected to the volatile logic element, the circuitry including a ferroelectric capacitor, the ferroelectric capacitor defining a voltage versus charge hysteresis curve, the circuitry including at least one isolating transistor that allows the ferroelectric capacitor to be selectively isolated from the node and a pre-charge circuit that can be used to pull down the voltage at the node, the circuitry adapted to set the position of the ferroelectric capacitor on the hysteresis curve depending on a value of the logic state at the node, wherein the value at the node is lost when the power to the apparatus is off and the circuitry is further adapted to restore the value of the logic state at the node of the volatile logic element using the ferroelectric capacitor when power is restored to the apparatus.   
     
     
       14. The apparatus of claim 13, wherein the isolating transistor is positioned with respect to the pre-charge circuit so that when the node of the volatile logic element is isolated from the ferroelectric capacitor, one side of the ferroelectric capacitor can set toward ground with the pre-charge circuit. 
     
     
       15. The apparatus of claim 1 wherein one end of the ferroelectric capacitor is connected to the isolating transistor. 
     
     
       16. A method comprising: operating a logic circuit including a volatile logic element, the volatile logic element having a node defining a logic state at a first time, the node of the logic element being connected to an input of another volatile logic element of the logic circuit;   storing the value of the node using a ferroelectric capacitor; and   after power to the volatile logic element is lost then restored, restoring a value at the node using the ferroelectric capacitor.   
     
     
       17. The method of claim 16, wherein the storing step includes using an isolating transistor to electrically connect and then isolate the node of the volatile logic element from the ferroelectric capacitor. 
     
     
       18. The method of claim 16, wherein one end of the ferroelectric capacitor is connected to a set line, wherein the storing step includes forcing the set line high, then low, while the node of the volatile logic element is electrically connected to the other end of the ferroelectric capacitor. 
     
     
       19. The method of claim 18, wherein the storing step includes setting the other end of the ferroelectric capacitor low. 
     
     
       20. The method of claim 19, wherein the storing step includes isolating the node of the volatile logic element from the other end of the ferroelectric capacitor, when the other end of the ferroelectric capacitor is set low. 
     
     
       21. The method of claim 16, wherein the restoring step comprises using more than one ferroelectric capacitors to store the value of multiple nodes. 
     
     
       22. The method of claim 16, wherein the restoring step comprises electrically connecting the other end of the ferroelectric capacitor to the node and pre-charging to set the nodes low. 
     
     
       23. The method of claim 16, wherein the restoring step comprises electrically connecting the other end of the ferroelectric capacitor to the node and pre-charging to set the nodes low. 
     
     
       24. The method of claim 23, wherein the restoring step further comprises stopping the pre-charge and forcing a set line attached to the ferroelectric capacitor high. 
     
     
       25. The method of claim 24, wherein the restoring step further comprises, thereafter, forcing the set line low. 
     
     
       26. The method of claim 25, wherein the restoring step further comprises electrically isolating the ferroelectric capacitor from the node and pre-charging the other end of the ferroelectric capacitor. 
     
     
       27. The method of claim 16, wherein the logic circuit is not part of a memory array and wherein the restoring step can be done without re-booting a central processing unit from the memory array. 
     
     
       28. The apparatus of claim 1, wherein the logic circuit is not part of a memory array and wherein the circuitry can restore the value of the node after a power failure without re-booting the central processing unit from a memory array. 
     
     
       29. The apparatus of claim 1, wherein the logic circuit is a central processing unit. 
     
     
       30. The apparatus of claim 1, wherein the logic circuit is an input/output circuit. 
     
     
       31. The apparatus of claim 13, wherein the logic circuit is not part of a memory array and wherein the circuitry can restore the value of the node after a power failure without re-booting the central processing unit from a memory array.