High-speed asynchronous memory with current-sensing sense amplifiers

Abstract

A high-speed current-sensing amplifier using process-insensitive matching of devices to determine the state of a bistable SRAM cell. The benefits include small voltage swings on heavily capacitively loaded bit lines and bit line bars during memory sensing, thereby maximizing the speed of the SRAM device. One embodiment uses a negative feedback amplifier minimize the bit line and bit line bar voltage swings while sensing current through matched PMOS transistors. Another embodiment uses cascoded PMOS devices to limit the swing of the bit lines and bit line bars, and a supply voltage and process-compensated voltage reference source to set the common-mode voltage of matched resistive sense elements. In all cases power on and off circuitry minimize the power of the memory device.

What is claimed is: 
     
       1. A current-sensing sense amplifier for a memory device having a power supply voltage, comprising: a bitline data input terminal, a bitline complement data input terminal, a Vref1 input terminal, a ground terminal and a memory data signal output terminal;   a first pair of PMOS transistors each having a source terminal connected to a respective one of said data input terminals, a drain terminal connected to said ground terminal, and a gate terminal;   a first pair of operational amplifiers each having an output terminal connected to the gate terminal, and an inverting input terminal connected to the source terminal, of a respective one of said first pair of PMOS transistors, and a non-inverting input terminal connected to said Vref1 input terminal; and   a voltage comparator having an inverting input terminal and a non-inverting input terminal each connected to the output terminal of a respective one of said operational amplifiers, and having an output terminal connected to said memory data signal output terminal.   
     
     
       2. A current-sensing sense amplifier as in claim 1 further comprising a first fixed reference voltage supply connected to said Vref1 input terminal. 
     
     
       3. A current-sensing sense amplifier as in claim 2 wherein the voltage of said first fixed reference voltage supply is substantially equal to 0.2 volts below said power supply voltage. 
     
     
       4. A current-sensing sense amplifier as in claim 2 further comprising: a Vref2 input terminal;   a second pair of PMOS transistors each having a source terminal connected to a respective one of said data input terminals, a drain terminal connected to said ground terminal, and a gate terminal; and   a second pair of operational amplifiers each having an output terminal connected to the gate terminal, and an inverting input terminal connected to the source terminal, of a respective one of said second pair of PMOS transistors, and a non-inverting input terminal connected to said Vref2 input terminal.   
     
     
       5. A current-sensing sense amplifier as in claim 4 further comprising a second fixed reference voltage supply connected to said Vref2 input terminal. 
     
     
       6. A current-sensing sense amplifier as in claim 5 wherein the voltage of said second reference voltage supply is between said first reference voltage and said power supply voltage. 
     
     
       7. A current-sensing sense amplifier as in claim 1 wherein each said operational amplifier has a power on/off enable input terminal, and powers on and off in response to different values of an enable signal being applied to said enable input terminal. 
     
     
       8. A current-sensing sense amplifier for a memory device having a supply voltage, comprising: a bitline data input terminal, a bitline complement data input terminal, a Vref3 input terminal, a ground terminal and a memory data signal output terminal;   a pair of PMOS transistors each having a source terminal coupled to a respective one of said data input terminals, a drain terminal, and a gate terminal;   a pair of resistors each having a first terminal connected to a respective one of said drain terminals and a second terminal connected to said ground terminal; and   a voltage comparator having an inverting input terminal and a non-inverting input terminal each connected to the drain terminal of a respective one of said PMOS transistors, and having an output terminal connected to said memory data signal output terminal.   
     
     
       9. A current-sensing sense amplifier as in claim 8, further comprising a fixed reference voltage supply connected to said Vref3 input terminal. 
     
     
       10. A current-sensing sense amplifier as in claim 9, wherein the voltage of said fixed reference voltage is substantially equal to 0.9 volts below said power supply voltage. 
     
     
       11. A current-sensing sense amplifier as in claim 8 wherein said fixed reference voltage source is power-supply-voltage-and-process-compensated. 
     
     
       12. A current-sensing sense amplifier as in claim 11 wherein said power-supply-voltage-and-process-compensated fixed reference voltage source circuit includes a current mirror circuit for supply voltage compensation. 
     
     
       13. A current-sensing sense amplifier as in claim 11 wherein said power-supply-voltage-and-process-compensated fixed reference voltage source circuit includes a current source containing duplicate devices for process compensation. 
     
     
       14. A method of sensing the state of a bistable memory cell with complementary bit lines, comprising: connecting to the bit lines via column select switches;   minimizing the voltage fluctuations at said column select switches by sinking the bit line currents through PMOS transistors driven by control means;   converting the currents flowing through said PMOS transistors to voltages by sensing means; and   comparing the resulting voltages by a voltage comparator.   
     
     
       15. The method of claim 14 wherein control means is negative feedback of two operational amplifiers. 
     
     
       16. The method of claim 15 wherein sensing means is output from said operational amplifiers. 
     
     
       17. The method of claim 14 wherein control means is a precision reference source. 
     
     
       18. The method of claim 17 wherein sensing means is two resistors.