Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device including a semiconductor substrate having a trench; a dielectric film formed on the substrate; a storage node electrode formed on the dielectric film; a first insulating film formed on the storage node electrode corresponding to the trench; a gate electrode formed on the first insulating film; a second insulating film formed on the gate electrode; a gate insulating film formed on at least one the side of gate electrode; a semiconductor layer formed on the at least one side of the first and second insulating films; and impurity regions formed in the semiconductor layer at the sides of the first and second insulating films. A manufacturing method including the steps of etching a semiconductor substrate to form a trench; forming a dielectric film and a conductive layer on the substrate; forming a first insulating film, a gate electrode, a second insulating film, and an interconnection layer, on the conductive layer corresponding to the trench; forming a semiconductor layer on the sides of the first and second insulating films; etching the conductive layer to form a storage node; and forming an impurity region in the semiconductor layer at the sides of the first and second insulating films.

What is claimed is: 
     
       1. A semiconductor memory device comprising: a semiconductor substrate having a trench;   a dielectric film formed on the substrate and in the trench;   a storage node electrode formed on the dielectric film and in the trench;   a first insulating film formed on the storage node electrode, wherein the first insulating film extends from within the trench to above the trench;   a gate electrode formed on the first insulating film;   a second insulating film formed on the gate electrode;   a gate insulating film formed at least on one side of the gate electrode;   a semiconductor layer formed on the gate insulating film at the at least one side of the gate electrode and also on the first and second insulating films; and   source and drain impurity regions formed in the semiconductor layer adjacent to the first and second insulating films, respectively.   
     
     
       2. The semiconductor memory device of claim 1, further comprising an interconnection layer formed on the second insulating film and connected to the drain impurity region. 
     
     
       3. The semiconductor memory device of claim 2, further comprising a bitline in contact with the interconnection layer. 
     
     
       4. The semiconductor memory device of claim 1, further comprising an insulating film formed between the substrate having the trench and the dielectric film in a region outside of the trench. 
     
     
       5. The semiconductor memory device of claim 1, wherein the semiconductor layer comprises a polysilicon film. 
     
     
       6. The semiconductor memory device of claim 1, wherein the source impurity region formed in the semiconductor layer is connected to the storage node. 
     
     
       7. The semiconductor memory device of claim 1, wherein a portion of the semiconductor layer adjacent to the gate electrode serves as a channel region. 
     
     
       8. The semiconductor memory device of claim 1, wherein a portion of the semiconductor substrate below the dielectric film is used as a plate electrode. 
     
     
       9. A semiconductor memory device comprising: a semiconductor substrate;   a first insulating film formed on the substrate;   a trench formed in the first insulating film and the substrate;   a dielectric film formed in the trench and on a portion of the first insulating film adjacent to the trench;   a storage node electrode formed in the trench on the dielectric film;   a second insulating film formed on the storage node electrode in the trench, wherein the second insulating film extends from within the trench to above the trench;   a gate electrode formed on the second insulating film;   a third insulating film formed on the gate electrode;   a gate insulating film formed at least on one side of the gate electrode;   a semiconductor layer formed on the gate insulating film at the at least one side of the gate electrode and also on the second and third insulating films; and   first and second impurity regions formed in the semiconductor layer adjacent to the first and second insulating films, respectively.   
     
     
       10. The semiconductor memory device of claim 9, further comprising an interconnection layer formed on the second insulating film and connected to the drain impurity region. 
     
     
       11. The semiconductor memory device of claim 10, further comprising a bitline in contact with the interconnection layer. 
     
     
       12. The semiconductor memory device of claim 9, wherein the semiconductor layer comprises a polysilicon film. 
     
     
       13. The semiconductor memory device of claim 9, wherein a portion of the semiconductor layer adjacent to the gate electrode serves as a channel region. 
     
     
       14. The semiconductor memory device of claim 9, wherein a portion of the semiconductor substrate below the dielectric film is used as a plate electrode. 
     
     
       15. A semiconductor memory device comprising: a first insulating film formed on a semiconductor substrate, and a trench formed in the first insulating film and the substrate;   a dielectric film formed in the trench and on a portion of the first insulating film adjacent to the trench;   a storage node electrode formed on the dielectric film;   a second insulating film formed on the storage node electrode, wherein the second insulating film fills the trench, and wherein the second insulating film has a width greater than a width of the trench;   a gate electrode formed on the second insulating film, wherein the gate electrode serves as a wordline;   a third insulating film formed on the gate electrode;   an interconnection layer formed on the third insulating film;   a bitline formed on the interconnection layer;   a gate insulating film formed as a sidewall on a side of the second insulating film, the gate electrode, and the third insulating film;   a channel layer formed as a sidewall on the gate insulating film, the third insulating film, and the interconnection layer;   first and second impurity regions formed in the channel layer, wherein the first impurity region is coupled to the storage node electrode, and the second impurity region is coupled to the interconnection layer; and   a fourth insulating layer, wherein the fourth insulating layer fills a space between the first insulating layer and the bitline.   
     
     
       16. The semiconductor memory device of claim 15, wherein the semiconductor substrate adjacent the dielectric film serves as a plate electrode. 
     
     
       17. The semiconductor memory device of claim 15, wherein the channel layer comprises a polysilicon film. 
     
     
       18. The semiconductor memory device of claim 15, wherein the fourth insulating layer comprises a borophosposilicate glass (BPSG). 
     
     
       19. The semiconductor memory device of claim 15 wherein the third insulating layer comprises a borophosposilicate glass (BPSG).