Programmable address decoder for programmable logic device

Abstract

For an FPGA having a configuration memory arranged in rows and columns, a programmable address decoder with a counter selects the order in which columns of memory cells will be programmed and selects which columns of memory cells are programmed. The decoder structure addresses a particular column only when an address provided by the counter matches an address in the memory cells of the decoder for that column. Bitstreams intended for older devices can be successfully loaded into newer devices. Bitstreams developed for future devices with additional features can be loaded into devices with fewer features, and the additional features are not used. The counter can be set to count not in sequential order so that if extra columns are provided, a defective column of the FPGA controlled by a corresponding column of configuration memory cells can be bypassed.

We claim: 
     
       1. For an FPGA having a configuration memory comprising configuration memory cells arranged in rows and columns, a programmable address decoder for addressing a column of said configuration memory cells comprising: a plurality of address memory cells for receiving an address bitstream;   a counter;   a decoder structure that addresses said column only when an address provided by said counter matches an address in said plurality of address memory cells.   
     
     
       2. A programmable address decoder as in claim 1 in which said plurality of address memory cells are connected into a shift register and loaded from a bitstream. 
     
     
       3. A programmable address decoder as in claim 2 wherein said FPGA is a second generation FPGA and said shift register comprises a first portion for holding an original address bit stream associated with features also present in a first generation FPGA and   a second portion for holding a new address bit stream associated with features not present in said first generation FPGA,   wherein corresponding features in said first and second generation FPGAs are configured to perform identical functions in response to identical first portions.   
     
     
       4. A programmable address decoder as in claim 1 wherein said plurality of address memory cells are grouped into a plurality of sets, one set of address memory cells associated with each column of said configuration memory to be addressed, and each address memory cell of one set corresponding to one output line from said counter. 
     
     
       5. A programmable address decoder as in claim 4 further comprising one set of XNOR gates corresponding to each set of address memory cells, and for each set, one XNOR gate receiving an output signal from a corresponding address memory cell and an output signal from said counter, and all XNOR gates in said set providing inputs to an AND gate for addressing a corresponding column of said configuration memory cells. 
     
     
       6. A programmable address decoder as in claim 4 wherein said counter includes at least one output line not associated with any memory cell of at least one of said sets. 
     
     
       7. A structure for configuring an FPGA from a bitstream of, comprising: a memory array divided into frames, each such frame having an address;   a data shift register capable of storing one frame of data;   a counter; and   a plurality of programmable address decoders, one such decoder being provided for each frame, each such decoder comparing the address of the associated frame to the value in said counter,   wherein one of said programmable address decoders loads a frame of data from said data shift register into a selected frame when said programmable address decoder associated with the selected frame indicates that the value in said counter matches the address of the selected frame, and   wherein the address value programmed into said address decoder is derived from the bitstream.