Circuit and method using data synchronization for battery power conservation in a paging receiver

Abstract

A battery saving circuit in a paging receiver operates in an idle mode and a batch mode. A power supply section generates operating power for the paging receiver. A receiving section receives paging information and converts the paging information into digital signals. A switching section provides operating power to the receiving section in response to a battery supply signal. A wordsync pattern detector connected to the receiving section detects wordsync periods during the batch mode, analyzes digital signals received at a starting interval of the wordsync period, and generates a wordsync pattern detection signal when wordsync pattern data is detected. The wordsync pattern data is made up of a predetermined number of bits within the digital signals received during the starting interval of the wordsync period. Operating power is provided during the starting interval of the wordsync period and is interrupted when the wordsync pattern detection signal is generated. Data received after the wordsync period is synchronized based on an ending position of the wordsync period.

What is claimed is: 
     
       1. A power saving circuit in a paging receiver, comprising: power supply means for generating operating power for said paging receiver;   means for receiving paging information and converting said paging information into a digital signal;   switching means for providing said operating power to said receiving means in response to a power supply signal;   wordsync pattern detecting means connected to said receiving means, for receiving said digital signal during batch periods, analyzing said digital signal received during an initial interval of a wordsync period of each of said batch periods, and generating a wordsync pattern detection signal when wordsync pattern data is detected from said digital signal received during said initial interval of said wordsync period, said wordsync pattern data being comprised of a predetermined sequence of data bits and said initial interval consisting of less than an entirety of said wordsync period; and   power controlling means for counting clock pulses generated during said batch periods to enable generation of said power supply signal during said initial interval of said wordsync period and to disable generation of said power supply signal when said wordsync pattern detection signal is generated, and for synchronizing reception of frame data during each of said batch periods by enabling generation of said power supply signal during a frame data period of each said batch period.   
     
     
       2. The power saving circuit as defined in claim 1, wherein said wordsync pattern detecting means comprises: means for storing said digital signal received during said initial interval of said wordsync period to generate first count data and detecting a starting point and an ending point of said initial interval of said wordsync period based on said first count data; and   means for decoding said first count data and generating said wordsync pattern detection signal when said first count data indicates detection of said wordsync pattern data.   
     
     
       3. The power saving circuit as defined in claim 2, wherein said power controlling means comprises: means for counting said clock pulses generated during said batch periods to generate second count data, said counting means being reset in response to generation of said wordsync pattern detection signal;   means for detecting starting and ending points of said frame data period and a starting point of said wordsync period by decoding said second count data;   means for selectively generating said power supply signal in response to an output signal from said detecting means; and   means for receiving said power supply signal, and delaying said power supply signal by a period equal to said wordsync period minus said initial interval of said wordsync period to synchronize reception of said frame data.   
     
     
       4. The power saving circuit as defined in claim 1, wherein said predetermined sequence of data bits comprises five bits of data. 
     
     
       5. A power saving circuit in a paging receiver, comprising: power supply means for generating operating power for said paging receiver;   means for receiving paging information and converting said paging information into a digital signal;   switching means for providing said operating power to said receiving means in response to a power supply signal;   wordsync detecting means connected to said receiving means, for receiving said digital signal during batch periods, analyzing said digital signal received during a wordsync period of each of said batch periods and generating a wordsync detection signal when said digital signal received during said wordsync period represents wordsync data;   wordsync pattern detecting means connected to said receiving means, for receiving said digital signal during said batch periods, analyzing said digital signal received during an initial interval of said wordsync period and generating a wordsync pattern detection signal when said digital signal received during said initial interval of said wordsync period represents wordsync pattern data, said wordsync pattern data being comprised of a predetermined sequence of initial bits of said wordsync data and said initial interval consisting of less than an entirety of said wordsync period; and   power controlling means for counting clock pulses generated during said batch periods to enable generation of said power supply signal at a starting point of said wordsync period, to disable generation of said power supply signal when said wordsync pattern detection signal is generated, to enable generation of said power supply signal when said wordsync pattern detection signal is not generated, and to disable generation of said power supply signal when said wordsync detection signal is generated, and for synchronizing reception of data during each said batch period by enabling generation of said power supply signal during a data frame period of each of said batch periods.   
     
     
       6. The power saving circuit as defined in claim 5, wherein said wordsync pattern detecting means comprises: means for storing said digital signal received during said initial interval of said wordsync period to generate first count data and detecting a starting point and an ending point of said initial interval of said wordsync period based on said first count data;   means for decoding said first count data and generating said wordsync pattern detection signal when said first count data indicates detection of said wordsync pattern data; and   means for latching said wordsync pattern detection signal to generate a wordsync selection signal in response to a latch clock signal generated at said ending point of said initial interval of said wordsync period.   
     
     
       7. The power saving circuit as defined in claim 6, wherein said power controlling means comprises: means for counting said clock pulses generated during said batch periods to generate second count data, said counting means being reset in response to generation of said wordsync pattern detection signal;   means for detecting starting and ending points of said frame data period and a starting point of said wordsync period by decoding said second count data;   means for selectively generating said power supply signal in response to an output signal from said detecting means;   means for generating a delayed power supply signal by delaying said power supply signal by a period equal to said wordsync period minus said initial interval of said wordsync period; and   means for receiving said power supply signal and said delayed power supply signal, providing said delayed power supply signal as said power supply signal when said wordsync pattern detection signal has been generated and providing said power supply signal when said wordsync detection signal has been generated.   
     
     
       8. The power saving circuit as defined in claim 7, wherein said wordsync detecting means comprises: means for storing said digital signal received during said wordsync period;   means for comparing said digital signal stored in said storing means with reference data to generate error data indicative of a number of error bits contained in said digital signal; and   means for generating said wordsync detection signal when said number of error bits contained in said digital signal is less than a predetermined number.   
     
     
       9. The power saving circuit as defined in claim 5, wherein said wordsync pattern data comprises five bits of data and said wordsync data comprises thirty-two bits of data. 
     
     
       10. The power saving circuit as defined in claim 8, wherein said wordsync pattern data comprises five bits of data and said wordsync data comprises thirty-two bits of data. 
     
     
       11. A power saving circuit in a paging receiver using a Post Office Code Standardization Advisory Group (POCSAG) code wherein battery power is selectively supplied to said paging receiver during a wordsync period of each batch period in response to a power supply signal, each said batch period being comprised of 17 data words, each said data word being comprised of 32 bits, said circuit comprising: controlling means for counting pulses of a data clock signal received during each said batch period to generate count data, generating a wordsync pattern period signal during a 5-bit period beginning at a starting point of said wordsync period based on said count data, and generating a wordsync period signal during a 32-bit period extending from said starting point of said wordsync period to an ending point of said wordsync period, said controlling means restarting said counting upon completion of each said batch period;   wordsync pattern detecting means for storing data received during said 5-bit period in response to said wordsync pattern period signal, and generating a wordsync pattern detection signal when said data received during said 5-bit period represents wordsync pattern data, said wordsync pattern data being comprised of a predetermined sequence of data bits;   batch mode executing means for counting said pulses of said data clock signal to enable generation of said power supply signal at said starting point of said wordsync period and disabling generation of said power supply signal in response to said wordsync pattern detection signal, said batch mode executing means restarting said counting in response to said wordsync pattern detection signal; and   synchronizing means for delaying said power supply signal when said wordsync pattern detection signal is generated, and synchronizing reception of a first said data word during a preset frame period by generating said power supply signal during said preset frame period.   
     
     
       12. The power saving circuit as defined in claim 11, wherein said wordsync pattern detecting means comprises: means for storing said data received during said 5-bit period in response to said wordsync pattern period signal; and   means for decoding said data stored in said storing means and generating said wordsync pattern detection signal when said data stored in said storing means represents said wordsync pattern data.   
     
     
       13. A method for saving battery power in a paging receiver having means for detecting a wordsync pattern signal comprised of a predetermined number of initial bits contained in a wordsync signal received during a wordsync period, said method comprising the steps of: providing battery power to said paging receiver at a starting point of said wordsync period while receiving said wordsync signal;   interrupting said battery power upon detection of said wordsync pattern signal during an initial interval of said wordsync period, with said initial interval consisting of less than an entirety of said wordsync period;   synchronizing reception of a frame signal by creating a delay period that extends from an ending point of said initial interval to an ending point of said wordsync period, said battery power being interrupted during said delay period;   maintaining interruption of said battery power from said ending point of said wordsync period to a starting point of a preset frame period;   providing said battery power to said paging receiver from said starting point of said preset frame period to an ending point of said preset frame period to enable said reception of said frame signal; and interrupting said battery power from said ending point of said preset frame period to a starting point of a next wordsync period.   
     
     
       14. The method for saving battery power as defined in claim 13, wherein said initial interval of said wordsync period represents a 5-bit period. 
     
     
       15. The method for saving battery power as defined in claim 14, wherein said wordsync period represents a 32-bit period. 
     
     
       16. A method for saving battery power in a paging receiver having means for detecting a wordsync pattern signal comprised of a predetermined number of initial bits contained in a wordsync signal, said method comprising the steps of: providing said battery power to said paging receiver while a preamble signal is detected;   detecting whether a wordsync detection signal corresponding to a first batch of data is generated while providing said battery power to said paging receiver, said wordsync detection signal indicating detection of an ending point of a wordsync period corresponding to said first batch of data;   interrupting said battery power in response to generation of said wordsync detection signal;   maintaining interruption of said battery power from said ending point of said wordsync period corresponding to said first batch of data to a starting point of a preset frame period corresponding to said first batch of data;   providing said battery power to said paging receiver from said starting point of said preset frame period corresponding to said first batch of data to an ending point of said preset frame period corresponding to said first batch of data to enable reception of frame data corresponding to said first batch of data;   interrupting said battery power from said ending point of said preset frame period corresponding to said first batch of data to a starting point of a wordsync period corresponding to a second batch of data;   providing said battery power to said paging receiver at a starting point of said wordsync period corresponding to said second batch of data;   interrupting said battery power when said wordsync pattern signal is detected during an initial interval of said wordsync period corresponding to said second batch of data;   synchronizing reception of frame data corresponding to said second batch of data by creating a delay period that extends from an ending point of said initial interval to an ending point of said wordsync period corresponding to said second batch of data, said battery power being interrupted during said delay period;   maintaining interruption of said battery power from said ending point of said wordsync period corresponding to said second batch of data to a starting point of a preset frame period corresponding to said second batch of data;   providing said battery power to said paging receiver from said starting point of said preset frame period corresponding to said second batch of data to an ending point of said preset frame period corresponding to said second batch of data to enable said reception of said frame data corresponding to said second batch of data; and   interrupting said battery power from said ending point of said preset frame period corresponding to said second batch of data to a starting point of a wordsync period corresponding to a third batch of data.   
     
     
       17. The method for saving battery power as defined in claim 16, wherein said initial interval of said wordsync period corresponding to said second batch of data represents a 5-bit period. 
     
     
       18. The method for saving battery power as defined in claim 17, wherein said wordsync period corresponding to said first, second and third batches of data represents a 32-bit period. 
     
     
       19. A power saving circuit in a paging receiver, comprising: power supply means for generating operating power for said paging receiver;   means for receiving paging information and converting said paging information into a digital signal;   switching means for providing said operating power to said receiving means in response to a power supply signal;   wordsync pattern detecting means connected to said receiving means, for receiving said digital signal during batch periods, analyzing said digital signal received during a first 5-bit interval of a 32-bit wordsync period of each of said batch periods, and generating a wordsync pattern detection signal when wordsync pattern data is detected from said digital signal received during said first 5-bit interval of said 32-bit wordsync period, said wordsync pattern data being comprised of a predetermined sequence of data bits; and   power controlling means for counting clock pulses generated during said batch periods to enable generation of said power supply signal during said first 5-bit interval of said 32-bit wordsync period and to disable generation of said power supply signal when said wordsync pattern detection signal is generated, and for synchronizing reception of frame data during each of said batch periods by enabling generation of said power supply signal during a frame data period of each of said batch periods.   
     
     
       20. The power saving circuit as defined in claim 19, wherein said wordsync pattern detecting means comprises: means for storing said digital signal received during said first 5-bit interval of said 32-bit wordsync period to generate first count data and detecting a starting point and an ending point of said first 5-bit interval of said 32-bit wordsync period based on said first count data; and   means for decoding said first count data and generating said wordsync pattern detection signal when said first count data indicates detection of said wordsync pattern data.   
     
     
       21. The power saving circuit as defined in claim 20, wherein said power controlling means comprises: means for counting said clock pulses generated during said batch periods to generate second count data, said counting means being reset in response to generation of said wordsync pattern detection signal;   means for detecting starting and ending points of said frame data period and a starting point of said 32-bit wordsync period by decoding said second count data;   means for selectively generating said power supply signal in response to an output signal from said detecting means; and   means for receiving said power supply signal, and delaying said power supply signal by a 27-bit period to synchronize reception of said frame data.   
     
     
       22. The power saving circuit as defined in claim 19, wherein said power controlling means comprises: means for counting said clock pulses generated during said batch periods to generate second count data, said counting means being reset in response to generation of said wordsync pattern detection signal;   means for detecting starting and ending points of said frame data period and a starting point of said 32-bit wordsync period by decoding said second count data;   means for selectively generating said power supply signal in response to an output signal from said detecting means; and   means for receiving said power supply signal, and delaying said power supply signal by a 27-bit period to synchronize reception of said frame data.   
     
     
       23. A method for saving battery power in a paging receiver, comprising the steps of: providing said battery power to said paging receiver at a starting point of a wordsync period while beginning reception of a 32-bit wordsync signal; interrupting said battery power after detecting a wordsync pattern signal during an initial interval of said wordsync period, said wordsync pattern data being comprised of a predetermined sequence of a first 5 bits of said 32-bit wordsync signal and said initial interval consisting of less than an entirety of said wordsync period;   creating a delay period that extends from an ending point of said initial interval to an ending point of said wordsync period, said battery power being interrupted during said delay period;   maintaining interruption of said battery power from said ending point of said wordsync period to a starting point of a preset frame period;   providing said battery power to said paging receiver from said starting point of said preset frame period to an ending point of said preset frame period to enable reception of a 32-bit frame signal; and interrupting said battery power from said ending point of said preset frame period to a starting point of a next wordsync period.   
     
     
       24. A power saving circuit in a paging receiver, comprising: power supply means for generating operating power for said paging receiver;   means for receiving paging information and converting said paging information into a digital signal;   switching means for providing said operating power to said receiving means in response to a power supply signal; and   a decoding unit in communication with said receiving means and adapted to receive said digital signal during batch periods, analyze said digital signal received during an initial interval of a wordsync period of each of said batch periods, generate a wordsync pattern detection signal when wordsync pattern data comprising a predetermined sequence of data bits is detected from said digital signal received during said wordsync pattern period, generate said power supply signal during said wordsync pattern period of said wordsync period and disable generation of said power supply signal when said wordsync pattern detection signal is generated, and synchronize reception of frame data during each of said batch periods by enabling generation of said power supply signal during a frame data period of each of said batch periods, with said initial interval consisting of less than an entirety of said wordsync period.   
     
     
       25. The power saving circuit of claim 24, wherein said decoding unit includes: a pattern detector in communication with said receiving means and adapted to respond to a pattern detector enabling signal by determining whether said digital signal received during said wordsync pattern period includes said wordsync pattern data and to generate a wordsync pattern detection signal when said wordsync pattern period includes said wordsync pattern data; and   a controller in communication with said pattern detector and adapted to generate said pattern detector enabling signal during a batch mode of said power saving circuit.   
     
     
       26. The power saving circuit of claim 25, wherein said controller is further adapted to receive a wordsync detection signal during an idle mode of said power saving circuit and to generate a batch mode enabling signal in response thereto, and wherein said decoding unit further includes a batch mode executing unit in communication with said controller and adapted to respond to said batch mode enabling signal by generating a batch mode signal during said frame data period of each of said batch periods, with said batch mode signal synchronizing said reception of frame data during each of said batch periods by enabling said generation of said power supply signal during said frame data period.