Apparatus and method for a party check logic circuit in a dynamic random access memory

Abstract

In a dynamic random access memory unit, a parity check logic circuit includes a parity signal generating circuit which generates a parity signal for each signal group transmitted on the input/output data bus. For a sequence of data groups on the data bus, a parity signal for each data group is generated, the parity signal combined with a parity signal generated for the previous data group or data groups. For a read operations, a parity signal is generated for each of sequence of retrieved data groups and combined with the parity signal(s) of the previous data groups of the sequence. The resulting parity signal is compared with the parity signal associated with the data group sequence and stored in the memory unit to generate a flag signal when the parity signals are not identical. For a write operation, the resulting parity signal for all the data groups is stored in memory unit at a location associated with the sequence of data groups. For a read-modify-write signal, the parity signal generated for each retrieved data signal is compared with the generated parity signal to be written into the memory location. When the signals do not match, the combined parity signal in the memory unit associated with the sequence including the retrieved and stored signal is changed to the opposite logic state.

What is claimed is: 
     
       1. A parity check circuit for use with a sequence of signal groups transmitted on a data bus, said circuit comprising: a parity signal generating unit coupled to said data bus for generating a parity signal determined by a signal group transmitted by said data bus;   a parity combining unit for combining a most recently generated parity signal with a stored parity signal to provide an updated stored parity signal;   a counter/gate unit for enabling transmission of said updated stored parity signal after transmission of said sequence of signal groups; and   a gate unit responsive to a write signal for transmitting said updated parity stored signal.   
     
     
       2. The parity check circuit of claim 1 wherein said counter/gate unit is responsive to a clock signal. 
     
     
       3. The parity check circuit of claim 1 further comprising: a comparison circuit, a first input terminal of said comparison circuit having an associated parity signal associated with said sequence of signal groups applied thereto; and   a gate unit responsive to a read signal for applying updated stored parity signal to said comparison unit, said comparison unit applying a flag signal to an output terminal when said updated stored parity signal and said associated parity signal are not identical.   
     
     
       4. The parity check circuit of claim 1 wherein said parity combining unit is configured as a comparison unit, said comparison unit providing an error signal when two consecutive data signal groups are applied to said data bus provide a different parity signal, said parity check circuit further comprising a gate unit coupled to a storage location and to said comparison unit for changing a logic signal stored in said storage location in response to said error signal and a read-modify-write signal. 
     
     
       5. The parity check circuit of claim 1 wherein said parity generating unit includes exclusive NOR logic gates. 
     
     
       6. The parity check circuit of claim 1 wherein said parity generating unit includes exclusive OR logic gates. 
     
     
       7. In a write operation, a method for checking parity of a sequence of data groups transmitted on a data bus, said method comprising the steps of: a.) generating a first parity signal for a first data group;   b.) storing said first parity signal as a stored parity signal;   c.) generating a next parity signal for a next sequential data group;   d.) combining said next parity signal with said stored parity signal to provide a combined data signal;   e.) storing said combined data signal as said stored parity signal;   f.) repeating steps c.) through e.) until a parity signal for a last sequential data group is combined with said stored parity signal to form a last combined parity signal; and   g.) storing said last combined parity signal in a memory location associated with said sequence of data groups for a write operation.   
     
     
       8. In a read operation, a method for comparing the parity of the sequence of read data groups with an associated parity signal associated with the stored sequence of data groups, said method comprising the steps of claim 7 wherein step g is replaced by: h.) in a read operation, comparing said last combined parity signal with an associated parity signal associated with said sequence of data groups; and   i.) generating a flag signal when said associated parity signal and said last combined parity signal are not identical.   
     
     
       9. In a read-modify-write operation for a sequence of data groups, a method for updating the parity of the sequence of data groups said method comprising the steps of: a.) retrieving an associated parity signal associated with said sequence of data groups and generating a next parity signal for a first data group of said sequence of data groups;   b.) after said first data group is modified, generating a modified parity signal for a modified first data group;   c.) comparing said modified parity signal with said next parity signal; and   d.) changing said associated parity signal to an opposite state when said modified parity signal is not the same as said next parity signal;   e.) after step d and when said next parity signal is the same as said modified parity signal, determining whether the data group modified was the last data group of the sequence;   f.) when the data group modified was not the last data group of the sequence, generating a next parity signal for a next data group in said sequence of data groups;   g.) after said next data group is modified, generating said modified parity signal and return to step c;   h.) in step e, when said most recent data signal group to be modified is the last data signal group of the sequence, storing said associated parity signal in association with said sequence of data signal that have been modified.   
     
     
       10. A parity checking circuit for use in a memory unit in which a plurality of sequential data groups are exchanged with a processing unit over a data bus, said circuit comprising: a parity generating unit coupled to said data bus and generating parity signal for a signal group being transmitted over said data bus;   a combining unit coupled to said parity generating unit for combining parity signals generated in response to said plurality of sequential data groups in response to a first control signal to provide a combined parity signal, said combining unit comparing each parity signal with a next sequential parity signal in response to a second control signal to provide a comparison signal;   comparison unit; and   a gate unit applying said combined parity signal to an output terminal in response to a write signal, said gate unit applying said combined signal to said comparison unit in response to a read signal.   
     
     
       11. The parity checking circuit of claim 10 wherein said comparison unit compares said combined parity signal generated in response to a sequence of data groups retrieved from said memory unit and a stored parity signal associated with said sequence of data groups retrieved from said memory unit, said comparison unit generating a flag signal when said comparison is false. 
     
     
       12. The parity checking circuit of claim 10 wherein said second control signal is a read-modify-write signal, said parity checking circuit further comprising a change means responsive to said comparison signal for altering a logic state of parity signal stored in said memory unit, said parity signal stored in said memory unit being associated with said data group to be modified. 
     
     
       13. The parity checking circuit of claim 10 wherein said parity generating unit is comprised of a plurality of exclusive OR logic gates. 
     
     
       14. The parity checking circuit of claim 10 wherein said gate circuit is responsive to CLK signals. 
     
     
       15. The parity checking circuit of claim 14 wherein said plurality of sequential data groups are synchronized with said CLK signals. 
     
     
       16. The parity checking circuit of claim 10 wherein said combining unit includes: a counter/register unit for storing parity signals,   an OR logic gate having a first input terminal coupled to said parity generating unit, and   a multiplexer applying an output signal from said OR gate to counter/register unit in response to said first control signal, said multiplexer applying an output signal from said parity generating circuit to said counter register unit in response to said second control signal.