Non-volatile memory system including apparatus for testing memory elements by writing and verifying data patterns

Abstract

A memory system which includes apparatus for efficiently performing parallel testing of the integrity of the memory cells contained in multiple memory devices. Each memory device or system is placed into a mode in which a desired test pattern is automatically written to each memory cell in each device. It is then verified that the data was written with the proper threshold voltage margin. The memory cells in each array are stepped through, address by address, and the data corresponding to the test pattern is written to each cell and then verified. After verification of the operation for a block of cells, a status bit is set to reflect successful completion of the test pattern write operation for the memory block.

I claim: 
     
       1. A memory system comprising: an array of memory cells;   a controller operable to control execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a first memory cell in the array, programs the first memory cell with data indicative of a logic value of zero, verifies the data programmed into the first memory cell, and performs an erase step on the memory cells; and   a test pattern data control circuit including a flow controller operable to alter execution of the memory erase operation during a test mode to bypass the erase step and execute the pre-programming operation using a test pattern input by a user.   
     
     
       2. The memory system of claim 1, wherein the flow controller further bypasses the memory erase sub-operations not involved in the regular pre-programming operation. 
     
     
       3. The memory system of claim 1, wherein the test pattern data control circuit further comprises: a test pattern data input circuit; and   a test pattern determiner operable to generate a second test pattern.   
     
     
       4. The memory system of claim 3, wherein the test pattern determiner further comprises: a data inverter operable to invert the input test pattern data to generate the second test pattern data.   
     
     
       5. The memory system of claim 3, wherein the test pattern determiner further comprises: a data modifier operable to modify the input test pattern data based on an incremented address to generate the second test pattern.   
     
     
       6. The memory system of claim 1, wherein the flow controller bypasses the memory erase sub-operations in response to control parameters stored in a data storage element of the memory system. 
     
     
       7. The memory system of claim 1, further comprising: an indicator which indicates success or failure of writing the test pattern during the altered memory erase operation.   
     
     
       8. A method of testing an integrity of memory cells contained in a memory array which is part of a memory device, the memory device including a controller operable to control execution of a memory erase operation which includes a plurality of memory erase sub-operations, the memory erase sub-operations including a regular memory pre-programming operation which accesses a first memory cell in the array, programs the first memory cell with data indicative of a logic value of zero, verifies the data programmed into the first memory cell, and performs an erase step on the memory array, the method comprising: inputting user specified test pattern data; and   modifying execution of the regular pre-programming operation during a test mode operation in response to a flow control circuit, so that the erase step is bypassed and a modified pre-programming operation is executed with the input test pattern data instead of the data programmed during the regular pre-programming operation.   
     
     
       9. The method of claim 8, further comprising: inverting the input test pattern data and executing the modified pre-programming operation on a second memory cell using the inverted test pattern data.   
     
     
       10. The method of claim 8, further comprising: modifying the input test pattern data based on an incremented address and executing the modified pre-programming operation on a second memory cell using the modified test pattern data.   
     
     
       11. The method of claim 8, further comprising: setting a bit in a status register indicating success or failure of the modified pre-programming operation.   
     
     
       12. A non-volatile memory device comprising: an array of non-volatile memory cells;   a controller operable to perform an erase function on the non-volatile memory cells by executing a sequence of steps including a pre-program step of writing the non-volatile memory cells to a programmed state prior to executing an erase step;   a test mode detector circuit for detecting a test mode initiation signal and initiating a test mode operation;   flow control circuitry adapted to modify the sequence of steps of the controller during the test mode operation such that the erase step is not performed by the controller, and the pre-program step writes an externally provided test pattern to the non-volatile memory cells in place of the programmed state executed during the erase function.   
     
     
       13. The non-volatile memory device of claim 12 wherein the flow control circuitry includes a flow register capable of storing data corresponding to the sequence of steps which can be performed by the controller. 
     
     
       14. The non-volatile memory device of claim 13 wherein the flow register is an eight bit register. 
     
     
       15. The non-volatile memory device of claim 12 further comprising: a data pattern inverter circuit for inverting the externally provided test pattern such that the pre-program step writes either the externally provided test pattern or the inverted test pattern to the non-volatile memory cells in place of the programmed state executed during the erase function.   
     
     
       16. The non-volatile memory device of claim 12 further comprising a status bit register for storing a status indicator indicating if the externally provided test pattern is successfully programmed during the test mode. 
     
     
       17. A method of testing a non-volatile memory device comprising the steps of: initiating a test mode of operation;   modifying a standard erase operation sequence during the test mode, such that a pre-program step and a pre-program verify step are performed, the modified standard erase operation sequence bypasses a normal erase step of the standard erase operation sequence;   receiving an externally supplied data test pattern;   performing the pre-program step using the externally supplied data test pattern; and   indicating if an error is detected during the pre-program verify step.   
     
     
       18. The method of claim 17 wherein the externally supplied data test pattern is written to an entire memory array. 
     
     
       19. The method of claim 17 further comprising the steps of: internally generating a second test pattern, such that the pre-program step alternately writes the externally supplied data test pattern and the second test pattern to memory cells of the non-volatile memory device.   
     
     
       20. The method of claim 17 wherein the error is indicated by setting a bit in a status register.