Logical check apparatus and method for semiconductor circuits and storage medium storing logical check program for semiconductor circuits

Abstract

A semiconductor circuit logical check apparatus including a unit for extracting information about laser trimming fuse elements based on layout data and logic-circuit diagram data of a semiconductor circuit, a unit for generating a command sequence indicating that some of the laser trimming fuse elements are broken on the basis of the extracted laser trimming fuse element information, a unit for generating error bit memory cell array models from memory cell array models, and a unit for executing, on a semiconductor circuit model, logic simulation on the basis of the command sequence.

What is claimed is: 
     
       1. A semiconductor circuit logical check apparatus for performing logical checks of a semiconductor circuit including laser trimming fuse elements and a memory cell array, said semiconductor circuit logical check apparatus comprising: laser trimming fuse element information extraction means for extracting information about said laser trimming fuse elements from a layout pattern data of said semiconductor circuit and logic-circuit diagram data of said semiconductor circuit;   laser trimming operation command sequence generating means for generating a laser trimming operation command sequence indicating that one or more of said laser trimming fuse elements are broken in said semiconductor circuit on the basis of said laser trimming fuse element information extracted by said laser trimming fuse element information extraction means;   error bit memory cell array generating means for generating, from memory cell array models associated with said memory cell array, error bit memory cell array models representing that an error bit is included in said memory cell array;   logic simulation executing means for executing logic simulation on models of said semiconductor circuit including said error bit memory cell array models on the basis of said laser trimming operation command sequence; and   output means for outputting results of said logic simulation.   
     
     
       2. The semiconductor circuit logical check apparatus as claimed in claim 1, further comprising laser trimming fuse element coordinate check means for checking coordinates of said laser trimming fuse elements using said layout pattern data of said semiconductor circuit and a control command file for laser trimming fuse element coordinate check, wherein said laser trimming fuse element information extraction means extracts information about laser trimming fuse elements whose coordinates obtained from said control command coincide with coordinates of said layout pattern data.   
     
     
       3. The semiconductor circuit logical check apparatus as claimed in claim 2, further comprising input means for inputting instructions from a user, wherein said laser trimming operation command sequence generating means generates a laser trimming operation command sequence only for information about laser trimming fuse elements selected by the user through said input means from said laser trimming fuse element information extracted by said laser trimming fuse element information extraction means.   
     
     
       4. The semiconductor circuit logical check apparatus as claimed in claim 3, further comprising input means for inputting instructions from a user, wherein said logic simulation executing means performs logic simulation on a portion selected by the user through said input means from said models of said semiconductor circuit including said error bit memory cell array models.   
     
     
       5. The semiconductor circuit logical check apparatus as claimed in claim 4, wherein said output means displays on a screen laser trimming fuse elements associated with laser trimming operation error and signal lines connected to said laser trimming fuse elements in a manner distinguishable from the remaining elements.   
     
     
       6. The semiconductor circuit logical check apparatus as claimed in claim 3, wherein said output means displays on a screen laser trimming fuse elements associated with laser trimming operation error and signal lines connected to said laser trimming fuse elements in a manner distinguishable from the remaining elements.   
     
     
       7. The semiconductor circuit logical check apparatus as claimed in claim 2, further comprising input means for inputting instructions from a user, wherein said logic simulation executing means performs logic simulation on a portion selected by the user through said input means from said models of said semiconductor circuit including said error bit memory cell array models.   
     
     
       8. The semiconductor circuit logical check apparatus as claimed in claim 7, wherein said output means displays on a screen laser trimming fuse elements associated with laser trimming operation error and signal lines connected to said laser trimming fuse elements in a manner distinguishable from the remaining elements.   
     
     
       9. The semiconductor circuit logical check apparatus as claimed in claim 2, wherein said output means displays on a screen laser trimming fuse elements associated with laser trimming operation error and signal lines connected to said laser trimming fuse elements in a manner distinguishable from the remaining elements.   
     
     
       10. The semiconductor circuit logical check apparatus as claimed in claim 1, further comprising input means for inputting instructions from a user, wherein said laser trimming operation command sequence generating means generates a laser trimming operation command sequence only for information about laser trimming fuse elements selected by the user through said input means from said laser trimming fuse element information extracted by said laser trimming fuse element information extraction means.   
     
     
       11. The semiconductor circuit logical check apparatus as claimed in claim 3, further comprising input means for inputting instructions from a user, wherein said logic simulation executing means performs logic simulation on a portion selected by the user through said input means from said models of said semiconductor circuit including said error bit memory cell array models.   
     
     
       12. The semiconductor circuit logical check apparatus as claimed in claim 11, wherein said output means displays on a screen laser trimming fuse elements associated with laser trimming operation error and signal lines connected to said laser trimming fuse elements in a manner distinguishable from the remaining elements.   
     
     
       13. The semiconductor circuit logical check apparatus as claimed in claim 10, wherein said output means displays on a screen laser trimming fuse elements associated with laser trimming operation error and signal lines connected to said laser trimming fuse elements in a manner distinguishable from the remaining elements.   
     
     
       14. The semiconductor circuit logical check apparatus as claimed in claim 1, further comprising input means for inputting instructions from a user, wherein said logic simulation executing means performs logic simulation on a portion selected by the user through said input means from said models of said semiconductor circuit including said error bit memory cell array models.   
     
     
       15. The semiconductor circuit logical check apparatus as claimed in claim 14, wherein said output means displays on a screen laser trimming fuse elements associated with laser trimming operation error and signal lines connected to said laser trimming fuse elements in a manner distinguishable from the remaining elements.   
     
     
       16. The semiconductor circuit logical check apparatus as claimed in claim 1, wherein said output means displays on a screen laser trimming fuse elements associated with laser trimming operation error and signal lines connected to said laser trimming fuse elements in a manner distinguishable from the remaining elements.   
     
     
       17. A semiconductor circuit logical check method for performing a logical check of a semiconductor circuit including laser trimming fuse elements and a memory cell array, said semiconductor circuit logical check method comprising: extracting information about said laser trimming fuse elements from a layout pattern data of said semiconductor circuit and a logic-circuit diagram data of said semiconductor circuit;   generating a laser trimming operation command sequence indicating that one or more of said laser trimming fuse elements are broken in said semiconductor circuit on the basis of said laser trimming fuse element information extracted;   generating, from memory cell array models associated with said memory cell array, error bit memory cell array models representing that an error bit is included in said memory cell array;   executing logic simulation on models of said semiconductor circuit including said error bit memory cell array models on the basis of said laser trimming operation command sequence; and   displaying results of said logic simulation.   
     
     
       18. A computer readable storage medium having a program causing a computer to execute the steps of: extracting information about laser trimming fuse elements from a layout pattern data of a semiconductor circuit and a logic-circuit diagram data of said semiconductor circuit, said semiconductor circuit including said laser trimming fuse elements and a memory cell array;   generating a laser trimming operation command sequence indicating that one or more of said laser trimming fuse elements are broken in said semiconductor circuit on the basis of said laser trimming fuse element information extracted;   generating, from memory cell array models associated with said memory cell array, error bit memory cell array models representing that an error bit is included in said memory cell array;   executing logic simulation on models of said semiconductor circuit including said error bit memory cell array models on the basis of said laser trimming operation command sequence; and   displaying results of said logic simulation.