Control circuit and method for a first-in first-out data pipeline

Abstract

Several designs of a stage for use in a FIFO pipeline are disclosed. Each stage includes a latch that is capable of latching a data element and capable of transitioning between a transparent state and an opaque state. The stages also include a control circuit capable of announcing the availability of the data element to the next stage as soon as the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element. In other words, if the latch of a stage is transparent and receives a signal Ri from the previous stage, the control circuit of the stage generates signal Ro after receiving signal Ri, thus enabling the next stage to latch the data element before the current stage has itself latched that data element. This feature is possible because the next stage receives at the input Din of latch block the same data element that appears at the input Din of the current latch block when the current latch block is transparent.

What is claimed is: 
     
       1. An apparatus, comprising: a latch capable of latching a data element and capable of transitioning between a transparent state and an opaque state; and   a control circuit capable of announcing the availability of the data element to a data destination after the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element; the control circuit further capable of directing the latch to abort the latching of the data element in the event that the data destination provides permission to send a second data element.   
     
     
       2. The apparatus of claim 1, wherein the control circuit is further capable of directing the latch to latch the data element in the event that the data destination does not provide permission to send the second data element. 
     
     
       3. The apparatus of claim 2, wherein the control circuit is further capable of directing the latch and the control circuit to transition from a Latching Requested state to an Unlatching Initiated state when the control circuits directing the latch to abort the latching of the data element. 
     
     
       4. The apparatus of claim 2, wherein the latch and the control circuit are further for sequencing through a Transparent state; a Latching Requested state; an Unlatching Initiated state and for returning to the Transparent state when the latching of the data element is aborted. 
     
     
       5. The apparatus of claim 1, wherein the control circuit is further capable of asserting a latch signal directing the latch to latch the data element. 
     
     
       6. The apparatus of claim 1, wherein the latch is further for asserting a latching initiated signal informing the control circuit that the latch has initiated latching of the data element. 
     
     
       7. The apparatus of claim 1, wherein the latch is further for asserting a latched signal informing the control circuit that the latch has latched the data element. 
     
     
       8. The apparatus of claim 1, wherein the latch and the control circuit are further for sequencing through a Transparent state; a Latching Requested state; a Latching Initiated state; a Latched state; an Unlatching Requested state; an Unlatching Initiated state and back to the Transparent state. 
     
     
       9. The apparatus of claim 1, wherein the control circuit is further for generating a signal for announcing to the data destination that the data element appearing at an output node of the latch is valid and available. 
     
     
       10. The apparatus of claim 1, wherein the control circuit is further for generating a signal which informs the data source it may send another data element to the latch. 
     
     
       11. The apparatus of claim 10, wherein the signal is generated when the latching of the data element is aborted. 
     
     
       12. The apparatus of claim 10, wherein the signal is generated when the data element is latched. 
     
     
       13. The apparatus of claim 10, further comprising an N stage FIFO including one stage comprising the latch and the control circuit. 
     
     
       14. The apparatus of claim 10, further including an N stage pipeline including one stage comprising the latch and the control circuit. 
     
     
       15. The apparatus of claim 1, wherein the latch comprises one or more latch circuits. 
     
     
       16. The apparatus of claim 1, wherein the latch includes a Schmitt trigger. 
     
     
       17. The apparatus of claim 1, wherein the control circuit comprises logic circuitry for generating a control signal for controlling the latch. 
     
     
       18. The apparatus of claim 1, wherein the control circuit comprises logic circuitry for asserting a communication signal to communicate with the data source. 
     
     
       19. The apparatus of claim 1, wherein the control circuit comprises logic circuitry for asserting a communication signal to communicate with the data destination. 
     
     
       20. The apparatus of claim 1, wherein the control circuit further comprises logic circuitry for receiving a signal from the data source. 
     
     
       21. The apparatus of claim 1, wherein the control circuit further comprises logic circuitry for receiving a signal from the data destination. 
     
     
       22. A method of providing a first-in-first out circuit, comprising the steps of: providing a latch capable of latching a data element and capable of transitioning between a transparent state and an opaque state; and   providing a control circuit capable of announcing the availability of the data element to a data destination after the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element, the control circuit further capable of directing the latch to abort the latching of the data element in the event that the data destination provides permission to send a second data element.   
     
     
       23. An method of operating a stage in a first-in-first-out (FIFO) circuit, comprising the steps of: introducing a data element to a latch of one stage in the FIFO, the latch being capable of transitioning between a transparent state and an opaque state;   announcing the availability of the data element to a data destination after the data element has propagated through the latch and without any latching or unlatching action of the latch prior to the announcement of the availability of the data element; and   directing the latch to abort the latching of the data element in the event the data destination provides permission to send a second data element.