MPEG2 transport decoder

Abstract

Disclosed is an MPEG2 transport decoder including a transport parser unit for storing each syntax field value by parsing, outputting each data identified with the packet identifier PID after collecting from each packet data and outputting the interrupt signal if a pointed resister value of the resist values is set; a CPU interface unit for providing an interface between the resister file of said transport parser unit and each decoder and outputting a signal selecting a transport parser unit or a video decoder, an audio decoder, a data decoder and a memory by decoding the address; a CPU for reading the interrupt resister from said CPU interface unit once an interrupt signal is inputted, detecting if the interrupt signal is inputted from said transport parser unit or from the video decoder, the audio decoder and the data decoder, and decoding according to the program on a memory unit; a memory unit for storing a program of the operations of said CPU; and a decoder interface unit for controlling in order to exchanging the data among said CPU, said transport parser unit and said video, audio, data decoders.

What is claimed is: 
     
       1. An MPEG2 transport decoder comprising a channel decoder unit for outputting a signal received through a satellite or a cable by tuning or duplicating to a transport packet data; a transport decoder for decoding the transport packet data; and video, audio and data decoders for decoding the video, audio and data signals by the transport decoder, said transport decoder further comprising: a transport parser unit for storing each syntax field value by parsing, outputting each data identified with the packet identifier (PID) after collecting from each packet data and outputting the interrupt signal if a pointed register value of register values is set;   a CPU interface unit for providing an interface between the resister file of said transport parser unit and each decoder and outputting a signal selecting a transport parser unit or a video decoder, an audio decoder, a data decoder and a memory by decoding the address;   a CPU for reading the interrupt register from said CPU interface unit once an interrupt signal is inputted, detecting if the interrupt signal is inputted from said transport parser unit or from the video decoder, the audio decoder and the data decoder, and decoding according to the program on a memory unit;   a memory unit for storing a program of the operations of said CPU; and   a decoder interface unit for controlling in order to exchange the data among said CPU, said transport parser unit and said video, audio, data decoders.   
     
     
       2. An MPEG2 transport decoder as defined in claim 1, wherein said transport parser unit comprises: a channel decoder interface unit for inputting/outputting the data and controlling signal with said channel decoder unit;   a transport decoder for storing each field value of each parsed header by parsing said MPEG2 transport packet syntax and interrupting the parsed field value to said CPU according to the condition of the interrupt register enable;   a memory unit for storing program specific information (PSI) sections of the MPEG2 streams, adaptation --  extension --  data, transport --  private --  data, pes --  extension --  data and digital storage media (DSM) --  trick --  mode --  data at addresses of the memory designated by the CPU;   an adaptation field (ADF) decoder for storing each field value of each parsed header by parsing the ADF data of said MPEG2 transport packet syntaxes and interrupting the parsed field value to said CPU according to the condition of the interrupt register enable; and   a packetized elementary stream (PES) decoder for storing each field value of each parsed header by parsing the PES section of said MPEG2 streams and interrupting the parsed field value to said CPU according to the condition of the interrupt register enable.   
     
     
       3. An MPEG2 transport decoder as defined in claim 2, wherein said transport decoder further comprises: a transport packet decoder controller for parsing the MPEG2 transport packet syntax; and   a transport packet decoder register for storing each header field value parsed in said transport packet decoder controller and the registers in said transport decoder register are accessed by said CPU.   
     
     
       4. An MPEG2 transport decoder as defined in claim 2, wherein said memory unit comprises: a memory for storing the PSI sections of the MPEG2 streams and the adaptation --  extension --  data, the transport --  private --  data, the PES --  extension --  data, and the DSM --  trick --  mode 13  data contained in the selected packet, and a memory controller having start addresses and end addresses for storing each PSI data, the adaptation --  extension --  data, the transport --  private --  data, the PES --  extension --  data and the DSM --  trick --  mode 13  data at designated addresses in the memory and for generating write addresses with automatic change of the write address starting from the start addresses to the end addresses for storing data, whereby the memory receives data and a control signal for storing the received data from the memory controller and allows the CPU access to the received data.   
     
     
       5. An MPEG2 transport decoder as defined in claim 2, wherein said ADF decoder comprises: an ADF decoder controller for parsing the ADF data of said MPEG2 transport packet syntaxes; and   an ADF decoder register for storing each field value of the parsed header in said ADF decoder controller and the registers in said ADF decoder registers are accessed by CPU.   
     
     
       6. An MPEG2 transport decoder as defined in claim 2, wherein said PES decoder comprises: a PES decoder controller for parsing the PES section of said MPEG2 streams; and   a PES decoder register for storing each field value of the parsed header and the registers in said PES decoder registers are accessed by CPU.   
     
     
       7. An MPEG2 transport decoder as defined in claim 1, wherein said CPU interface unit comprises: a data buffer for performing a buffering to read/write the contents of said CPU data bus;   a CPU address decoder for generating a selecting signal for selecting a register of said transport parser unit by decoding the high address part of said CPU, a selecting signal for accessing the video, audio and other decoders and a selecting signal for accessing the program/data memory;   a transport (tp)-CPU interface unit for generating a controlling signal cntrl-dsp-td for said CPU to access the register in the transport packet decoder register by incorporating a controlling signal of the CPU with the address signal and the selecting signal;   a memory interface unit for generating a controlling signal cntrl-dsp-mem for the CPU to access the register in the memory controller by incorporating a controlling signal of the CPU with an address signal and a selecting signal;   an adf-CPU interface unit for generating a controlling signal cntrl-dsp-adf for the CPU to access the register in the ADF decoder register by incorporating a controlling signal of the CPU with an address signal and a selecting signal; and   a pes-CPU interface unit for generating a controlling signal cntrl-dsp-pes for the CPU to access the register in the PES decoder register by incorporating a controlling signal of the CPU with an address signal and a selecting signal.   
     
     
       8. An MPEG2 transport decoder as defined in claim 7, wherein said tp-CPU interface unit, memory interface unit and adf-CPU interface unit decode each address for each register to have other address. 
     
     
       9. An MPEG2 transport decoder as defined in claim 1, wherein said decoder interface unit comprises: a video decoder interface unit for controlling a controlling signal for the CPU and the PES decoder to access the video decoder jointly;   an audio decoder interface unit for controlling a controlling signal for the CPU and the PES decoder to access the audio decoder jointly; and   a data decoder interface unit for controlling a controlling signal for the CPU and the PES decoder to access the data decoder jointly.   
     
     
       10. An MPEG2 transport decoder as defined in claim 9, wherein said video, audio and data decoder interface units comprise: a first data buffer for outputting after storing momentarily the outputted data;   a memory unit for storing the data outputted from said transport parser unit and then outputting firstly the data inputted before, simultaneously with outputting the signals fifo-ef and fifo-ff indicating if the data is filled out or not;   a second data buffer for outputting the data outputted from said memory unit after storing momentarily;   an access controlling unit for setting the signal token giving right of an access to said CPU according to the decoder accessing condition of the CPU and the outputting signals fifo-ef and fifo-ff from said memory unit; and   an interface controlling unit for controlling said CPU access to read/write the video decoder after finishing the present accessing job with receiving the signal token from said access controlling unit.   
     
     
       11. An MPEG2 transport decoder as defined in claim 9, wherein said video, audio and data decoder interface units can be partially composed in accordance with the application. 
     
     
       12. An MPEG2 transport decoder as defined in claims 9 or 10, wherein said video, audio and data decoder interface units are organized with sharing the memory unit. 
     
     
       13. An MPEG2 transport decoder as defined in claim 12, wherein said memory unit comprises: a third data buffer for storing the output data of said transport parser unit momentarily;   a memory being divided into three areas of video, audio and data storing areas and storing the data inputted from said third data buffer or outputting the stored data as the decoder data;   a video writing pointer for outputting a writing address in order to write the video data to said memory;   an audio writing pointer for outputting a writing address in order to write the audio data to said memory;   a data writing pointer for outputting a writing address in order to write the data to said memory;   a first address buffer for storing momentarily the address outputted from said video writing pointer;   a second address buffer for storing momentarily the address outputted from said audio writing pointer;   a third address buffer for storing momentarily the address outputted from said data writing pointer;   a video reading pointer for outputting a reading address in order to read the video data to said memory;   an audio reading pointer for outputting a reading address in order to read the audio data to said memory;   a data reading pointer for outputting a reading address in order to read the data to said memory;   a fourth address buffer for storing momentarily the address outputted from said video reading pointer;   a fifth address buffer for storing momentarily the address outputted from said audio reading pointer;   a sixth address buffer for storing momentarily the address outputted from said data reading pointer; and   a memory interface controller for controlling the operations of said video, audio and data reading/writing pointers and said first to sixth address buffers by the controlling signal cntrl5 from the PES decoder.   
     
     
       14. An MPEG2 transport decoder including a channel decoder unit for outputting a signal received through a satellite or a cable by tuning or duplicating to transport packet data; a transport decoder for decoding the transport packet data; and video, audio and data decoders for decoding video, audio and data signals by the transport decoder, said transport decoder further comprising: transport parser means for storing each syntax field value by parsing, outputting each data identified with the packet identifier (PID) after collecting from each packet data and outputting the interrupt signal if a pointed register value of register values is set;   CPU interface means for providing an interface between a register file of said transport parser means and each of said video, audio and data decoders;   CPU means for reading an interrupt register from said CPU interface means once an interrupt signal is inputted;   said memory means for storing a program of the operations of said CPU means; and   decoder interface means for controlling the exchanging of data among said CPU means, said transport parser means and said video, audio, and data decoders.   
     
     
       15. The MPEG2 transport decoder according to claim 14, wherein the CPU interface means further comprises: an output for outputting a signal selecting said transport parser means or one of said video, audio, and data decoders and said memory means by decoding the address.   
     
     
       16. The MPEG2 transport decoder according to claim 15, wherein the CPU means further comprises: a detector portion for detecting if the interrupt signal is inputted from said transport parser means or from one of the video, audio, and the data decoders, and a decoder portion for decoding according to the program on said memory means.   
     
     
       17. An MPEG2 transport decoder comprising: first means for storing a program, reading an interrupt register, detecting a portion of the transport decoder providing an interrupt signal to said first means, and performing a decoding operation in accordance with the program;   second means for parsing an MPEG2 transport packet syntax and controlling an address bus, a data bus and a controlling signal for said first means; and   interface means for providing an interface between said first means and said second means.