Semiconductor component for high voltage

Abstract

A high frequency MOS transistor structure with an extended drift region, which modulates the resistance in the drift region of the MOS transistor. The extended gate layer is obtained by an extra semiconductor layer forming a second MOS structure on top of a thin gate oxide layer. The electrical field will then be uniformly distributed laterally in the extended drift region. This design makes it possible to produce a MOS transistor with a short channel length and an extended drift region with low doping concentration and still having very low on-resistance together with a high breakdown voltage.

What is claimed is: 
     
       1. A device forming a high voltage MOS transistor structure comprising a substrate with a n -  doped semiconductor layer having a first n +  doped drain area and a p doped body containing a second n +  doped region and a first p +  doped region forming a source area, said n -  doped layer providing a drift channel between said drain and source areas, wherein on top of said drift channel an insulating gate oxide layer is disposed having on top a semiconductor layer which together with the insulating gate oxide layer forms an extended gate layer, whereby a diode is connected between said drain area and a third n +  doped region in said extended gate layer. 
     
     
       2. The device according to claim 1, wherein said extended gate layer further comprises a p -  doped region, a second p +  doped region and a fourth n +  doped region forming a MOS structure on top of said insulating gate oxide. 
     
     
       3. The device according to claim 1, wherein said substrate is a p -  doped semiconductor. 
     
     
       4. The device according to claim 1, wherein said substrate is an insulator formed by sapphire or the like. 
     
     
       5. The device according to claim 1, wherein a silicon dioxide layer, forming a buried SOI layer, separates said n -  doped semiconductor layer from an underlying substrate. 
     
     
       6. The device according to claim 1, wherein said diode is a suitable external semiconductor diode connected between said first n +  doped region in said n -  doped semiconductor layer and said third n +  doped region of said extended gate layer. 
     
     
       7. The device according to claim 1, wherein said diode is a semiconductor diode integrated between said first n +  doped region in said n -  doped semiconductor layer and said extended gate layer whereby said third n +  doped region may be part of the integrated diode. 
     
     
       8. The device according to claim 1, wherein said second n +  doped region and said first p +  doped region forming the source area are provided with separate contact pads. 
     
     
       9. The device according to claim 1, wherein said second p +  doped region and said fourth n +  doped region forming a source area of said extended gate layer are provided with separate contact pads. 
     
     
       10. A device forming a high voltage MOS transistor structure comprising a substrate with a p -  doped semiconductor layer having a first p +  doped drain area and a n doped body containing a second p +  doped region and first n +  doped region forming a source area, said p -  doped layer providing a drift channel between said drain and source areas, wherein on top of said drift channel an insulating gate oxide layer is disposed having on top a semiconductor layer which together with the insulating gate oxide layer forms an extended gate layer, whereby a diode is connected between said drain area a third p +  doped region in said extended gate layer. 
     
     
       11. The device according to claim 10, wherein said extended gate layer further comprises a n -  doped region, a second n +  doped region and a fourth p +  doped region forming a MOS structure on top of said insulating gate oxide. 
     
     
       12. The device according to claim 10, wherein said substrate is a n -  doped semiconductor. 
     
     
       13. The device according to claim 10, wherein said substrate is an insulator formed by sapphire or the like. 
     
     
       14. The device according to claim 10, wherein a silicon dioxide layer, forming a buried SOI layer, separates said p -  doped semiconductor layer from an underlying substrate. 
     
     
       15. The device according to claim 10, wherein said diode is a suitable external semiconductor diode connected between said first p +  doped region in said p -  doped semiconductor layer and said third p +  doped region of said extended gate layer. 
     
     
       16. The device according to claim 10, wherein said diode is a semiconductor diode integrated between said first p +  doped region in said p -  doped semiconductor layer and said extended gate layer whereby said third p +  doped region may be part of the integrated diode. 
     
     
       17. The device according to claim 10, wherein said second p +  doped region and said first n +  doped region forming the source area are provided with separate contact pads. 
     
     
       18. The device according to claim 10, wherein said second n +  doped region and said fourth p +  doped region forming a source area of said extended gate layer are provided with separate contact pads.