Semiconductor device and production method therefor

Abstract

A semiconductor device to which two kinds of electric voltage can be supplied comprises: a first MOS transistor formed in the first well having a first conduction type and being fixed to a first electric potential, a second MOS transistor formed in a second well having a second conduction type different from the first one and being fixed to a second electric potential higher than the first electric potential, and a third well formed between the first and second wells having the second conduction type and being fixed to a ground electric potential. The first MOS transistor comprises a first gate oxide film having a prescribed thickness and a first gate electrode having a prescribed gate length, while the second MOS transistor comprises a second gate oxide film having a thickness larger than the prescribed thickness of the first gate oxide film and a second gate electrode having a gate length longer than the prescribed thickness of the first gate length.

What is claimed is: 
     
       1. A semiconductor device comprising: a semiconductor substrate;   a first complementary MOS transistor formed in said semiconductor substrate, said first complementary MOS transistor being driven under a first power supply voltage;   a second complementary MOS transistor formed in said semiconductor substrate, said second complementary MOS transistor being driven under a second power supply voltage higher than the first power supply voltage; and   a well formed between said first and second complementary MOS transistors in said semiconductor substrate, said well being fixed to a prescribed voltage.   
     
     
       2. The device according to claim 1, wherein thicknesses of gate oxide films of P-channel and N-channel MOS transistors in said second complementary MOS transistor are larger than those of gate oxide films of P-channel and N-channel MOS transistors in said first complementary MOS transistor, and gate lengths of the P-channel and N-channel MOS transistors in said second complementary MOS transistor are longer than those of the P-channel and N-channel MOS transistors in said first complementary MOS transistor. 
     
     
       3. The semiconductor device according to claim 2, wherein the first voltage is 3.3 volts, the second voltage is 5 volts, and said well is fixed to a ground potential. 
     
     
       4. The semiconductor device according to claims 1, wherein P-channel and N-channel MOS transistors in said first complementary MOS transistor are formed in first and second wells having different conduction types from each other, and P-channel and N-channel MOS transistors in said second complementary MOS transistor are formed in third and fourth wells having different conduction types from each other. 
     
     
       5. The device according to claim 4, wherein thicknesses of gate oxide films of P-channel and N-channel MOS transistors in said second complementary MOS transistor are larger than those of gate oxide films of P-channel and N-channel MOS transistors in said first complementary MOS transistor, and gate lengths of the P-channel and N-channel MOS transistors in said second complementary MOS transistor are longer than those of the P-channel and N-channel MOS transistors in said first complementary MOS transistor. 
     
     
       6. The device according to claim 4, wherein the first voltage is 3.3 volts, the second voltage is 5 volts, and said well is fixed to a ground potential. 
     
     
       7. A method for fabricating a semiconductor device comprising the steps of: forming a plurality of islands in a semiconductor substrate for defining first to fifth regions successively in the semiconductor substrate;   injecting first ions into the second and fourth regions to form second and fourth wells having a first conduction type;   injecting second ions different from the first ions into the first, third and fifth regions to form first, third and fifth wells;   injecting further ions into the first and second regions so as to make a threshold voltage of MOS transistors to be formed in the first and second regions the same as those of MOS transistors to be formed in the fourth and fifth regions;   forming a first complementary MOS transistor in the first and second wells;   forming an electrode in the third well to be fixed to a ground potential; and   forming a second complementary MOS transistor in the fourth and fifth wells to which a power supply voltage higher than that of the first complementary MOS transistor is applied.   
     
     
       8. The method according to claim 7, wherein in the step of forming the second complementary MOS transistor, thicknesses of gate oxide films of P-channel and N-channel MOS transistors in said second complementary MOS transistor are formed to be larger than those of gate oxide films of P-channel and N-channel MOS transistors in said first complementary MOS transistor, and gate lengths of the P-channel and N-channel MOS transistors in said second complementary MOS transistor are formed to be longer than those of the P-channel and N-channel MOS transistors in said first complementary MOS transistor. 
     
     
       9. The method according to claim 8, wherein the steps of forming the first and second complementary MOS transistors comprises the steps of: oxidizing all active areas at the same time to form oxide films;   covering the active areas of a resist pattern of the fourth and fifth areas with a resist pattern;   removing the oxide films only at the first, second and third wells by using the resist pattern as a mask; and   oxidizing all active areas at the same time to form oxide films, so that thicknesses of the oxide films at the active areas of the fourth and fifth regions are larger than those of the oxide films at the active areas of the first and second regions.